m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 194

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.3
2.3.1
2.3.2
28529-DSH-001-K
2–1
7–4
3–0
Bit
Bit
7
6
5
4
3
0
Default
Default
pppp
0000
00
0
0
0
0
0
0
General Control Registers
0xF00—GENCTRL (General Device Control Register)
0xF01—PARTNUM (Part and Version Number Register)
DevMstRst
DevLgcRst
EnStatLat
EnCntrLat
EnIntPin
OneSecOut
PartNum[3:0]
Version[3:0]
Name
Name
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Device master reset. When set high, all internal state machines in the TC block are held in reset
and all registers (except this bit) assume their default values. If configuring the device for
pass-through operation, a minimum delay of 25 uS for IMA_Sysclk of 66 MHz or 33uS for
IMA_Sysclk of 50 MHz is required from the release of device reset to the first access of the
IMA_RX_TRANS_TABLE register or IMA_RX_ATM_TRANS_TABLE register (0x818/0x819).
Device logic reset. When set high, all internal state machines in the TC block are held in reset
but register values are unaffected.
When set to 1, the one-second status latching is enabled. The value of the status bits are the
events which occurred between the last two one-second events. Any events occurring after the
last one-second event is not reflected when the status register is read. Those events are
reflected in the status register upon the next one-second event. When a status register is read,
the status is cleared and is not updated until the next one-second event.
When set to 0, the one-second status latching is disabled. The value of a status register is the
events occurred since the last read of the status register.
When set to 1, the one-second counter latching is enabled. The value of the counter is the
number of events counted between the last two one-second events. Any events occurring after
the last one-second event is not reflected when the counter is read. Those events are reflected
in the counter upon the next one-second event. When a counter is read, the count is cleared
and is not updated until the next one-second event.
When set to 0, the one-second counter latching is disabled. The value of a counter is the
number of events counted since the last read of the counter.
Enables the MicroInt* output pin.
Reserved, set to zero.
When set to 1, the OneSecIO pin is configured as an output. The pin provides a one-second
event pulse. The one-second event is generated internally of the device. The event occurs after
the device has counted 8000 periods of a 8 KHz clock.
When set to 0, the OneSecIO pin is configured as an input. The one-second event must be
generated externally, by pulsing the OneSecIO pin for low-high-low.
Part number controlled by bondout:
16 TC Port version - 0101
32 TC Port version - 1001
Version number of the device. Number starts at “0000” for the initial version
®
Description
Description
Registers
179