m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 206

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

2.4.5
This register contains some of the basic IMA Subsystem configuration.
2.4.6
Registers 0x805—0x808 are used to perform memory diagnostic tests on the internal or external differential delay
SRAM.
28529-DSH-001-K
5–4
7–0
Bit
Bit
7
6
3
2
1
0
Default
Default
0x00
—
0
0
0
0
0
0
0x804—IMA_MISC_CONFIG (IMA Miscellaneous Control)
0x805—IMA_MEM_LOW_TEST (IMA Memory Test Address (Bits 0–7))
Alternate GTSM Mode
PHY Size
Enable External HEC
Checker
Check ATMUTxAddr[4] and
ATMURxAddr[4]
Check ATMUTxAddr[3] and
ATMURxAddr[3]
Check ATMUTxAddr[2] and
ATMURxAddr[2]
Memory Test Address
Name
Name
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
This field contains the least significant bits of the memory test address for the selected memory
component. Range: 0x00–0xFF
Reserved. Set to 0
1 = When the GTSM is down, ATMUTxClAv for that group is controlled as if all configured
links in the group are Active.
0 = When the GTSM is down, ATMUTxClAv for that group is inactive.
This two bit field determines the use of the PHY side ClAv and Enb* signals. When using
Utopia-to-Serial mode, PHY Size should be set to 16 ports per Clav and En*. Thus for
M28525, PHY Size should be 2 while for M28529, PHY Size should be 1.
1 = Bit 7 of the HEC Byte is a HEC error flag
0 = Use the HEC Error checker within the IMA block
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[4] and TMURxAddr[4] for correct value
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[3] and ATMURxAddr[3] for correct value
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[2] and ATMURxAddr[2] for correct value
0 = ClAv and En* for every 4 PHY addresses (support 8 ports total)
1 = ClAv and En* for every 16 PHY addresses (support 32 ports total)
2 = ClAv and En* for all PHY addresses (support 32 ports total)
3 = ClAv and En* for every 8 PHY addresses (support 16 ports total)
high when PHY Size is set to 2.
(Ports 0-3 assigned to Clav0/Enb0*)
(Ports 4-7 assigned to Clav1/En1*)
(Ports 0-15 assigned to Clav0/Enb0*)
(Ports 16-31 assigned to Clav1/Enb1*)
(Ports 0-31 assigned to Clav0/Enb0*)
(Ports 0-7 assigned to Clav0/Enb0*)
(Ports 8-15 assigned to Clav1/Enb1*)
For Utopia-to-Utopia mode, PhyUrxEna[1] and PhyUtxEna[1] should be pull
®
Description
Description
Registers
191