ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 70

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Table 30. ORT82G5 Memory Map (Continued)
Lattice Semiconductor
SERDES Global Control Registers (Read Write) Act on all Four Channels in SERDES Quad A or SERDES Quad B.
30005 - A
30105 - B
30006 - A
30106 - B
Control Registers (Read/Write), xx=[AA,...,BD]
30800 - Ax
30900 - Bx
30801 - Ax
30901 - Bx
Absolute
Address
(0x)
[2]xC
[3]xD
[6]xC
[7]xD
[2]xC
[3]xD
[6]xC
[7]xD
[0]xA
[1]xB
[4]xA
[5]xB
[0]xA
[1]xB
[4]xA
[5]xB
[0:4]
[6:7]
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[5]
Reserved
GMASK_[A:B]
GSWRST_[A:B]
GPWRDNT_[A:B]
GPWRDNR_[A:B]
Reserved
Not used
GTESTEN_[A:B]
TestMode[A:B]
Not used
Reserved
ENBYSYNC_xx
LCKREFN_xx
LOOPENB_xx
NOWDALIGN_xx
Name
descrip.
Reset
Value
(0x)
See
00
00
bit
Reserved, must be set to 0. Set to 0 on device reset.
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of all channels in the SERDES quad are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of all four
channels, except that the device configuration settings are not affected
when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device
reset.
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for all four channels of are powered down to con-
serve power. The GPWRDNT_[A:B] bit overrides the individual
PWRDNT_xx bits. GPWRDNT_[A:B] = 0 on device reset.
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for all four channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
Reserved, 1 on device reset.
Not used. 0 on reset.
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of all four channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
TestMode - See Test Mode section for settings
Not used
Reserved
ENBYSYNC_xx = 1 Enables Receiver Byte Synchronization for Channel
xx. ENBYSYNC_xx = 0 on device reset.
LCKREFN_xx = 0 Locks the receiver PLL to ref reference clock for
Channel xx.
LCKREFN_xx =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xx = 0 on device reset.
Enable Loopback Mode for Channel xx. When LOOPEN_xx=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xx=0 on device reset.
Word Align Disable Bit. When NOWDALIGN_xx=1, receiver word align-
ment is disabled for Channel xx. NOWDALIGN_xx=0 on device reset.
70
ORCA ORT42G5 and ORT82G5 Data Sheet
Description