ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 24

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 8. Receive DEMUX Block for a Single SERDES Channel
One clock per block of two or four channels, called RCK78[A,B], is sent to the FPGA. The control bits RCKSEL[A,B]
are used to select the channel that is the source for these clocks.
Link State Machines
Two link state machines are included in the device, one for XAUI applications and a second for Fibre Channel appli-
cations.
The Fibre Channel link state machine is responsible for establishing a valid link between the transmitter and the
receiver and for maintaining link synchronization. The machine is initially in the Loss Of Synchronization (LOS)
state upon power-on reset. This is indicated by WDSYNC_xx = 0. While in this state, the machine looks for a partic-
ular number of consecutive idle ordered sets without any invalid data transmission in between before declaring syn-
chronization achieved. Achievement of synchronization is indicated by asserting WDSYNC_xx = 1. Specifically, the
machine looks for three continuous idle ordered sets without any misaligned comma character or any running dis-
parity based code violation in between. In the event of any such code violation, the machine would reset itself to the
ground state and start its search for the idle ordered sets again. A typical valid sequence for achieving link synchro-
nization would be K28.5 D21.4 D21.5 D21.5 repeated three times.
In the synchronization achieved state, the machine constantly monitors the received data and looks for any kind of
code violation that might result due to running disparity errors. If it were to receive four such consecutive invalid
words, the link machine loses its synchronization and once again enters the loss of synchronization state (LOS). A
pair of valid words received by the machine overcomes the effect of a previously encountered code violation. LOS
is indicated by the status of WDSYNC_xx output which now transitions from 1 to 0. At this point the machine
attempts to establish the link yet again. Figure 9 shows the state diagram for the Fibre Channel link state machine.
LOS is also indicated by DEMUXWAS_xx status register bit. This bit is set to 0 during loss of synchronization.
SRBDxx[9:0]
RWD_xx[23:16]
RWD_xx[31:24]
RWD_xx[15:8]
RWBIT8_xx[1]
RWBIT9_xx[1]
RWBIT8_xx[2]
RWBIT9_xx[2]
RWBIT8_xx[0]
RWBIT9_xx[0]
RWBIT8_xx[3]
RWBIT9_xx[3]
RWD_xx[7:0]
10-bit
p
q
LATENCY = 4 RSYS_CLK [A1,...,B2] CLOCKS
r
s
t
x
24
y
ORCA ORT42G5 and ORT82G5 Data Sheet
z
p
q
s
r
7-0
7-0
7-0
7-0
40-bit
p
q
s
r
8
8
8
8
p
q
s
r
9
9
9
9
x
t
y
z
7-0
7-0
7-0
7-0
x
t
y
z
8
8
8
8
x
z
t
y
9
9
9
9