ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 19

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplifies both the signal
and the noise at the receiver
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis
can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass
transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in
Table 3.
Table 3. Preemphasis Settings
Receive Path (Backplane to FPGA) Logic
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a
10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters,
detects code violations and aligns the bit stream to the proper word boundary.
As shown in Figure 6, the basic blocks in the receive path include:
Receive SERDES Block
• CML input buffer
• Receive PLL
• 1:10 demultiplexer (DEMUX)
• Clock and Data Recovery (CDR) section
• 10b/8b decoder
• 1:4 demultiplexer and Embedded Core/FPGA interface
• 1:4 DEMUX
• Low speed parallel Embedded Core/FPGA logic interface
• Multi-channel alignment logic
PE1
0
0
1
1
PE0
H(z) = (1 – az
0
1
0
1
19
0% (No Preemphasis)
12.5%
12.5%
25%
ORCA ORT42G5 and ORT82G5 Data Sheet
Amount of Preemphasis (a)
–1
)
(1)