ort82g5 Lattice Semiconductor Corp., ort82g5 Datasheet - Page 65

• Manufacturer Part Number: ort82g5
• Description: Xaui And Fc Fpscs
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
30933
Status Registers (Read Only, Clear on Read), xx = [AC, AD, BC or BD]
30804 - Ax
30904 - Bx
30805 - Ax
30905 - Bx
30814 - A
30914 - B
Absolute
Address
(0x)
[0:3]
[4:5]
[0:1]
[2:3]
[4:5] XAUISTAT_xC
[6:7] XAUISTAT_xD
[2:3]
[5:7]
Bit
[0]]
[6]
[7]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[4]
SYNC2_[A:B]_OVFL
SYNC2_[A:B]_OOS
DEMUXWAS_xC
DEMUXWAS_xD
CH24_SYNC_xC
CH24_SYNC_xD
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
Reset
Value
(0x)
00
00
00
00
XAUI Status Register. Status of XAUI link state machine for Channel xC
00 – No synchronization, 10 – Synchronization done, 11 – Not used, 01
– no_comma (see XAUI state machine) and at least one CV detected.
XAUISTAT_xC[0:1] = 00 on device reset.
XAUI Status Register. Status of XAUI link state machine for Channel xD
00 – No synchronization, 10 – Synchronization done, 11 – Not used, 01
– no_comma (see XAUI state machine) and at least one CV detected.
XAUISTAT_xD[0:1] = 00 on device reset.
Status of Word Alignment. When DEMUX_WAS_xC=1, word alignment
is achieved for Channel xC. DEMUX_WAS_xC=0 on device reset.
Status of Word Alignment. When DEMUX_WAS_xD=1, word alignment
is achieved for Channel xD. DEMUX_WAS_xD=0 on device reset.
Status of Channel Alignment. When CH24_SYNC_xC=1, multi-channel
alignment is achieved for Channel xC. CH24_SYNC_xC=0 on device
reset.
Status of Channel Alignment. When CH24_SYNC_xD=1, multi-channel
alignment is achieved for Channel xD. CH24_SYNC_xD=0 on device
reset.
Multi-Channel Overflow Status. When SYNC2_[A:B]_OVFL=1, twin
channel synchronization FIFO overflow has occurred.
SYNC2_[A:B]_OVFL=0 on device reset.
Multi-Channel Out-Of-Sync Status. When SYNC2_[A:B]_OOS=1, twin
channel synchronization has failed.
SYNC2_[A:B]_OOS=0 on device reset.
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ORCA ORT42G5 and ORT82G5 Data Sheet
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Description