emc643sp16ak Emlsi Inc., emc643sp16ak Datasheet - Page 18

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emc643sp16ak

Manufacturer Part Number
emc643sp16ak
Description
4mx16 Bit Cellularram Ad-mux
Manufacturer
Emlsi Inc.
Datasheet
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
(except A[19:18])
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
collisions require a corresponding number of additional CE# LOW cycles.
A/DQ[15:0]
A[19:18]
LB#/UB#
A[21:16]
ADV#
WAIT
WE#
CRE
CLK
OE#
CE#
2
High-Z
Latch control register value
t
CSP
t
t
t
t
SP
OPCODE
SP
SP
SP
OPCODE
t
KHTL
t
t
t
HD
t
HD
HD
HD
Note3
Latch control register address
18
t
CBPH
High-Z
Address
Address
Address
4Mx16 CellularRAM AD-MUX
Valid
data
EMC643SP16AK
Don’t Care

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