w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 71

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
IRQ Break Event Enable 0 Register (default = 00h)
Function:
Type:
Bit Description:
WINBOND ELECTRONICS CORP. AMERICA
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
This power management register may only be used while the W83C554F is in x86 mode.
Read/Write
IRQ7. Enable IRQ7 as Break Event. When this bit is "1," IRQ7 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ6. Enable IRQ6 as Break Event. When this bit is "1," IRQ6 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ5. Enable IRQ5 as Break Event. When this bit is "1," IRQ5 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ4. Enable IRQ4 as Break Event. When this bit is "1," IRQ4 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ3. Enable IRQ3 as Break Event. When this bit is "1," IRQ3 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ2. Enable IRQ2 as Break Event. When this bit is "1," IRQ2 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ1. Enable IRQ1 as Break Event. When this bit is "1," IRQ1 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
IRQ0. Enable IRQ0 as Break Event. When this bit is "1," IRQ0 as Break Event detection is
enabled. Upon detection, PMACT# is de-asserted.
Register Information
69