w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 59

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
PCI Control Register (default = 20h)
Type:
Bit Description:
WINBOND ELECTRONICS CORP. AMERICA
4.1.2
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Function 0 Control Registers
Read/Write
Reserved. This read only bit is set to "0".
Reserved.
IAE. Interrupt Acknowledge Enable. Setting this bit allows the W83C554F chip to respond to
the interrupt acknowledge command. This bit is active after reset.
Reserved. This read only bit is set to "0".
ESDP. Early Subtractive Decoding Point. Setting this bit will move the subtractive decoding
point one PCI clock earlier from "slow" to "medium" timing.
PWE. Post Write Enable. Setting this bit will allow PCI memory write cycles to the ISA bus to
be posted.
RETRYE. Retry Enable. When this bit is set to "1", PCI slave cycles are retried following PCI
2.1 delayed transaction rule. When this bit is reset to "0" and the internal bus is busy, a PCI
slave cycle will be held in wait states until the bus becomes idle and the access completes.
The default state of this bit after a hardware reset is "0".
PCI NMI Enable. When set, PCI error status bits in the Status Register (except SSE) will
generate an NMI. Defaults to "0".
Register Information
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