w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 130

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
The Bus Master IDE Register set is defined by the PCI SIG. It is composed of 16 8-bit registers and is located at the I/O
address specified by Base Address Register 4. The registers can be accessed 8, 16, 24, or 32 bits at a time.
This register set is supplied to offer a higher performance lower overhead IDE disk protocol. With this protocol, the host
(PCI) transfers will be bus master cycles and the IDE device transfers will be DMA. The normal PIO protocol uses I/O
transfers on both the host and IDE interfaces. Primary and Secondary refer to the primary and secondary IDE ports. Both
register sets are identical.
Offset from
Base Address
03h - 00h
07h - 04h
0Bh - 08h
0Fh - 0Ch
Note: The registers shown in Table 4-5 cannot be accessed until after Base Address Register 4 is written (with any non zero
value).
WINBOND ELECTRONICS CORP. AMERICA
4.4
Bus Master IDE (Function 1) I/O Registers
31
Reserved
Reserved
Table 4-5. Bus Master IDE I/O Register Organization
24
23
Primary Status
Register
Secondary Status
Register
Primary PRD Table Address
Secondary PRD Table Address
Register Bits
16
15
Reserved
Reserved
8
Register Information
7
Primary Command
Register
Secondary Command
Register
0
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