w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 36
w83c554f
Manufacturer Part Number
w83c554f
Description
System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W83C554F.pdf
(156 pages)
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W83C554F
System Architecture
3.7
PCI I/O Write Cycle
Bursting is not supported by the W83C554F for I/O cycles, so a target disconnect will be executed after the first data transfer
on all I/O Write commands to prevent multiple I/O data phases.
Refer to Figure 3-3. The Slave I/O Write command (C/BE[3:0]# = 3h during address phase) is used by the processor to
write the W83C554F internal bus master registers, IDE device, and ISA registers or X-bus registers. It is a single, non-burst,
8, 16 or 32-bit transfer cycle, initiated by the CPU. It is a fixed duration, i.e. the W83C554F will assert TRDY# on the 4th
bus cycle of the transfer when accessing the internal bus master registers. It will have a variable duration when accessing an
IDE device or ISA register.
Figure 3-3. Slave I/O Write
WINBOND ELECTRONICS CORP. AMERICA
34
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