w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 133

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
4.4.3
(Base Address Register 4 value + offset: 07h-04h, 0Fh-0Ch)
These registers contain the starting address of the first Physical Region Descriptor of the Descriptor Table in memory when
W83C554F is functioning as a PCI bus master with one or more multi-word DMA mode disk drives. Bits 31 through 2
define a doubleword aligned address in memory. Bits 1 and 0 are reserved and will be ignored on writes and read as 00b.
The information in the Descriptor Table controls where the data is transferred to/from system memory, how much data is
transferred (Byte Count) and when the transfer is complete (EOT bit).
The Descriptor Table is composed of one or more Physical Region Descriptors. Each entry is two doublewords (8 bytes) and
is defined below.
The Memory Region Physical Base Address specifies a word aligned address in memory that the bus master will transfer data
to/from.
The Byte Count specifies the number of bytes of data to transfer for this region of memory. The byte count is required to be
even (D0=0b). The maximum number of bytes defined in one descriptor entry is 64K which is indicated by a value of 00h.
The number of bytes specified must not cause the memory region specified to cross a 64K boundary.
Bit 31 of doubleword 1 is the End Of Table flag. Bus master operation terminates upon completion of the descriptor entry
that has EOT set.
The Physical Region Descriptor Table cannot cross a 64K memory boundary.
WINBOND ELECTRONICS CORP. AMERICA
Primary/Secondary PRD Table
Dword
0
1
31
Memory Region Physical Base Address (31:2)
EOT
Table 4-6. Physical Region Descriptor
Reserved
16
Data Bits
15
Byte Count
Register Information
10
00
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