w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 15

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
WINBOND ELECTRONICS CORP. AMERICA
Pin Name
PAR
FRAME#
PERR#
IRDY#
TRDY#
DEVSEL#
STOP#
IDSEL
Pin #
60
53
58
54
55
56
57
40
Table 2-2 (Continued). PCI Bus Signals
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Description
Parity. Even parity across AD[31:0] and C/BE[3:0]#. PAR is valid
one clock after the address phase. For data phases, PAR is valid one
clock after either IRDY# is asserted on the write transaction, or
TRDY# is asserted on a read transaction. PAR remains valid until
one clock after the completion of the current phase. PAR is driven
only for read data phases, and checked during write data phases.
Cycle Frame. Indicates the start and duration of an access. It is
asserted to indicate the start of a bus transaction; during which data
transfers continue. When FRAME# is de-asserted, the transaction is
in the final data phase.
PCI Parity Error.
Initiator Ready. Indicates the initiating agent's ability to complete
the current transaction's data phase. It is used jointly with TRDY#.
During a write, it indicates that valid data is present on AD[31:0].
During a read cycle, it indicates the master is prepared to accept
data.
Target Ready. Indicates the target's ability to complete the current
data phase of the transaction. It is used with IRDY#. During a read
cycle, it indicates that valid data is present on AD[31:0]. During a
write cycle, it indicates the target is prepared to accept data.
Device Select. This signal is asserted by the W83C554F when it is
acting as a target in a transaction. It is an input when the W83C554F
is acting as the initiator of a transaction.
Stop. This is asserted to terminate the current transaction. It causes a
disconnect condition, limiting slave I/O cycles to one data transfer
since I/O burst transfers are not supported. During master cycles, it
indicates the target wants to terminate the cycle.
Initialization Device Select. Chip select signal, used during PCI
configuration read and write cycles.
Pin Descriptions
13