w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 52

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
Break events include IRQ0 - IRQ15, DRQ0 - DRQ7, SERR#, ISA IOCHK#, INTR and non-maskable interrupts to the CPU
(NMI). OEM designers can program Function 0 PCI Configuration Registers 60h - 63h to select individual IRQs and DRQs
as the break events. These registers allow the W83C554F to function within a comprehensive power management scheme
with an external power management unit (as located on CPU-to-PCI bridge devices) in a green PC application.
The W83C554F incorporates two different CPU modes which change the functionality of several pins on the chip. An x86
mode supports any Intel-compatible microprocessor, including Pentium, AMD K5, Cyrix M1, NexGen 586, Intel P6, and
others. A PowerPC mode supports the IBM/Apple/Motorola PowerPC microprocessor Common Hardware Reference
Platform, as well as other RISC CPUs, such as DEC Alpha, Sun SPARC, and MIPS R4xxx CPUs.
Following is a summary of pins which change functionality depending on which CPU mode is chosen for the W83C554F via
strapping pin 8 high (PowerPC) or low (x86) with a weak (2.2K ohm) resistor:
It can be seen from the above table (and the respective pin descriptions on pages 12-25) that the W83C554F is able to
generate all of the required reset signals for the microprocessor, PCI bus, and ISA bus when in PowerPC (non-x86) mode.
WINBOND ELECTRONICS CORP. AMERICA
3.23
3.24
Break Events
CPU Modes (X86 or PowerPC)
Pin #
4
5
22
116
118
119
x86 Function
IGNNE#
PMACT#
A20M#
XRD#
XCS1
XCS0
PowerPC Function
HRESET#
ISARST
PCIRST#
SECURITY/XRD#
X8XCS
ROMCS
System Architecture
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