lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 35

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lrs1302

Manufacturer Part Number
lrs1302
Description
8m Flash And 1m Sram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
NOTES:
2. kcws~dhEs
3. Block erases, byte writes, and lock-bit configurations
4. Automatic
5. CMOS inputs are either V,-c- +0.2V or GNDk0.2V.
6. Sampled,
7. Master lock-bit set operations
8. m connection
1. All currents are in RMS unless otherwise noted.
VoH2
VP,,
V,,
V, .KO
VI-II-I
block-lock
the device’s current draw is the sum of kms
range between VPPx(Max>
when the master lock-bit is set and Rp=V,.
SHARI=
Output
V,, Lockout during
Normal
VP, during Byte Write,
Block Erase or Lock-Bit
Operations
V,,
Rp Unlock Voltage
cMos)
not 100% tested.
bit is set and P=VIH.
Lockout Voltage
Power Savings @F’S) reduces typical ~C-J to 3mA at 3.3V V,- in static operation.
High Voltage
Operations
to a V,
are specified with the device de-selected.
supp 1 y is allowed for a Maximum
and VP&&n)
are inhibited
3,6
7,;
6
DC Characteristics
and above VP&Max).
when D=V,,.
Block erases and byte writes are inhibited
LRS13023
or kcEs and &--
V,,
Vcc
0.85
11.4
-0.4
2.7
2.0
TTL inputs are either V, or V,.
are inhibited
12.6
3.6
1.5
If read or byte written while in erase suspend mode,
Block lock-bit configuration
cumulative
(Continued)
or &--JJ, respectively.
when VPPIvPPx,
V
V
V
V
V
V
period of 80 hours.
v,-=v,,Min
TA=O to 85°C
Set master lock-bit
Override
&=-2.5uA
and not guaranteed
when the corresponding
master and block lock-bit
operations
are inhibited
in the
. .
33

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