lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 22

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

JO Clear Block Lock-Bits Command
J set block lock-bits
Iear
)&bit
nly the Clear Block Lock-Bits command.
>ck-bit is set, clearing block lock-bits requires both the
Ilear Block Lock-Bits
lin. See Table
oftware write protection
Ilear
No-cycle command
etup is first written.
le device automatically
fhen
ompletion
nalyzing
Vhen the operation
R5 should be checked. If a clear block lock-bit error is
.etected, the status register
XJI will remain
nother command
his
xecution
Lock-Bits
Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Block Erase or
Operation
two-step
Block
block
read
SHARP
not set, block lock-bits
status register bit SR7.
ensures
of the clear block
(see Figure
Lock-Bits
lock-bits
6 for a summary
sequence
in read status register
is issued.
Lock-Bit
Master
sequence. A clear block lock-bits
that
is complete,
command
After the command
X
X
0
0
1
are cleared in parallel
1
operation
command.
options.
outputs
9). The CPU
block
of
should
Lock-Bit
set-up
Block
can be cleared using
and V,
X
lock-bits
X
X
X
X
status register
0
1
lock-bits
is executed
status register
of hardware
With
be cleared. The
Table 6. Write Protection
followed
If the master
mode until
the master
can detect
on the m
is written,
event by
V,
V,
V, or
.v,
-.
VHH
are
w.
VHH
VW
VW
VW
VW
V,,
V,,
VTW
VW
RF
via the
LRS13023
by a
or
or
data
and
not
bit
by
Master Lock-Bit Override.
Block Erase and Byte Write Enabled
Block is Locked. Block Erase and Byte Write Disabled
Block Lock-Bit Override.
Enabled
Set Block Lock-Bit
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
Master Lock-Bit Override.
Set Master Lock-Bit Disabled
Set Master Lock-Bit
Clear Block Lock-Bits Enabled
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
block
SR.1 and SR.5 will be set to “1” and the operation
If a clear block lock-bits
VP, or Vcc transitioning
active transition,
undetermined
required
values. Once the master lock-bit
cleared.
accidentally
command
SR.4 and SR5 being set to “1”. Also, a reliable
Vcc=VccI
operation
SR.5 will be set to “1”. In the absence of this high
voltage,
against alteration.
operation
if the master
attempted
fail. A clear block
<V,
attempted.
Alternatives
produce
lock-bits
to initialize
the block
requires that the master lock-bit
is attempted
sequence will result in status register
with the master lock-bit
and VPP=VPP,.
cleared. An invalid
Enabled
Enabled
state. A repeat of clear block lock-bits is
lock-bit
spurious
operation
block lock-bit
Block Erase and Byte Write
Effect
A successful clear block lock-bits
lock-bits
Clear Block Lock-Bits
Set Block Lock-Bit Enabled
block lock-bit
lock-bits
is set, that m=V,.
while
operation
results
out of valid
If a clear block lock-bits
can
operation
content
V+V,,,
Clear Block Lock-Bits
values are left in an
and should
is set, it cannot be
only
contents to known
is aborted
set and i?is=VIH,
are protected
with
range or Rp
occur
is not set or,
SR.3 and
VI&@
If it is
not be
due to
when
clear
will
bits
20