lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 30
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lrs1302
Manufacturer Part Number
lrs1302
Description
8m Flash And 1m Sram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1302.pdf
(61 pages)
_____
5 DESIGN CONSIDERATIONS
i.1 Three-Line
The device will often be used in large memory
SHARPprovides
nultiple
xovides for:
To use these control
iecoder
:onnected to all memory
READ control
nemory devices have active outputs while deselected
nemory devices are in standby mode. y
:onnected
prevent
ran&ions.
system reset.
i.2
?ash memory
:areful
nterested
urrent levels, active current levels and transient peaks
rroduced by falling
Transient current
a. Lowest possible memory power dissipation.
b. Complete
not occur.
Power Supply Decoupling
SHARP
device
unintended
should
memory
in three supply
to the system
POWERGOOD
assurance that data bus contention
power switching
Output Control
line. This assures that only selected
decoupling.
three control inputs to accommodate
enable
magnitudes
connections.
and rising edges of m and m.
writes
inputs
m
devices and the system’s
should also toggle during
POWERGOOD
current
during
System
efficiently,
while
depend on the device
characteristics
Three-line
issues; standby
m
system
designers
an address
should
should be
signal
require
control
arrays.
power
LRS13023
wilI
are
be
to
pin supplies
and block erasing. Use similar
considerations
V,
voltage spikes and overshoots.
suppress transient voltage peaks. Each device shouId
have a 0.1 uF ceramic capacitor connected between its
V,,
high-frequency,
placed
Additionally,
electrolytic
power supply connection
bulk capacitor
by PC board &ace inductance.
5.3 V,, Trace on Printed Circuit Boards
Updating
system requires that the printed
pay attention
outputs’
control and proper decoupling
supply
and GND and between its V,, and GND. These
as close
capacitive
flash memories
capacitor
traces and decoupling
the memory
to the V,, Power supply
given to the V,,
for every
will overcome
low inductance
as possible
and inductive
should be placed at the array’s
between Vc- and GND. The
cell current for byte writing
eight
that reside
trace widths and layout
voltage
capacitor selection will
circuit board designer
power bus. Adequate
capacitors
devices,
to
will decrease V,,
loading.
package
slumps
trace. The V,,
in the target
a 4.7 pF
should be
Two-line
caused
leads.