lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 21

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.8 Byte Write Suspend Command
The Byte Write Suspend
interruption
locations.
the Byte Write
WSM
predetermined
continues
after the Byte Write
Polling
when the byte write
read data from
block-lock
(both will be set to “1”). Specification
the byte write suspend latency.
At this point, a Read Array command
suspended. The only other valid commands
write is suspended
Write Resume. After Byte Write Resume command
written
the byte write process. Status register bits SR.2 and
SR7 will
Resume command
outputs status register
VP, must remain at V,,
byte write) while
must also remain
used for byte write).
4.9 Set Block and Master Lock-Bit Commands
A flexible
enabled
master lock-bit.
erase operations
not set, individual
Set Block Lock-Bit
zommand,
master
subsequent setting of block lock-bits requires both the
Set Block Lock-Bit
see Table 6 for a summary
write protection
status register bits SR.7 and SR.2 can determine
suspend
SHARP
to the flash memory,
lock-bit.
via a combination
Once the byte write process starts, writing
to output
automatically
bit modification.
block
in conjunction
to read data in other
Suspend
point
The block lock-bits gate program
options.
locations
the
After
locking
at VrH or V,
block lock-bits can be set using the
command.
command
is written,
while
in byte write suspend mode.
are Read Status Register and Byte
status register
Suspend
operation
in the algorithm.
data when read (see Figure 7).
byte
the master
clear. After the Byte Write
command
command
(the same VP, level used for
the master
and unlocking
other than that which
of hardware and software
with
of block lock-bits
With the master lock-bit
and V,
the device automatically
write
The Set Master Lock-Bit
the WSM will continue
command
has been suspended
i@=V,,
(the same Rp level
allows byte write
requests that the
data when read
sequence
can be written to
lock-bit
twHRHl defines
flash
on the m pin.
lock-bit
The device
is written.
while byte
scheme is
memory
sets the
is set,
and a
LRS13023
at a
gates
and
m
is
is
Set block lock-bit and master lock-bit are executed by a
two-cycle command
lock-bit
address
lock-bit
locked)
device
lock-bit
read (see Figure 8). The CPU can detect the completion
SR.7.
When
register
CUT will remain
This
will result in z&us
vcc=vccl
is set, that Rp=V&.
lock-bit
results and should not be attempted.
master lock-bit operation
attempted
operations
results and should not be attempted.
device automatically
of the set lock-bit event by analyzing
detected,
new comman d is issued.
execution
set. An invalid
set to “1”. Also; reliable
voltage,
alteration.
A successful set block lock-bit .operation
the master lo&bit
“1” and the operation
operations
“1” and the operation
two-step
the set lock-bit
confirm (and an address within the block to be
address).
setup along with appropriate
or the set master
algorithm.
set and; RP=VIH,
bit SR.4 should
is written
lock-bit
the status register
ensures that lock-bits
with Rp=V,,,
and ‘V+=VPPH.
while
with
Set Block or Master Lock-Bit command
sequence
in read status register mode until
The WSM
VIHcRR<V,
be cleared or, if the master lock-bit
~V,,<RP<V,
After the sequence is written,
contents
followed
sequence. The set block or master
register bits SR.4 and SR.5 being
outputs status register data when
Eit is attempted
operation
-
will
-
will
:
operations
requires that m=V,.
SR.l and SR.4 will be set to
SR.l and SR.4 will be set to
be checked.
ln the absence of this high
lock-bit
of
fail. Set master
by either the set block
should
are .protected
fail. Set block
then
set-up
are not accidentally
:produce
is complete,
produce
confirm
occur only when
controls
status register bit
be cleared. The
A successful set
with the master
block or device
I
If an error
followed
requires
(and any
spurious
spurious
lock-bit
lock-bit
the set
against
status
If it is
that
the
by
19
is
a