lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 31

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

5.4 V,,,
3lock erase, byte write and lock-bit
lot guaranteed
ange, V,
N,,
)it SR3 is set to “1” along with SR4 or SR5, depending
m the attempted
luring
:onfiguration,
ti
nay
:ommand
operation
ransitions
The GUI latches co mmands
md is not altered by V,
~tions.
ifter
ransitions
After block erase, byte write, or lock-bit configuration,
?ven after V,,
nust be placed in read array mode via the Read Array
:ommand
iesired.
5.5 Power-Up/Down
The device
t&dental
:onfiguration
>ower-up, the device is indifferent
upply
‘esets the GUI to read array mode at power-up.
enter deep power-down.
or V,,.
leave
exit
(V,, or V,,)
Its state is read array mode upon power-up,
V,,, i?is Transitions
block
if subsequent
to V,, clear the status register.
below Vu0
sequence must be repeated
block
is
from
falls outside of a valid Vccl range, or RP
is designed
data
If V,,
the operation
restored.
during
transitions
if Vpp fails outside
erase,
erasure,
deep
operation.
partially
powers-up
error is detected, status register
Protection
access to the memory
power-down
power
byte
Device
to offer protection
or a
byte
issued by system software
down to V,,,,
will abort and the device
altered.
If Rp transitions
The aborted operation
first. Internal
write,
writing,
transitions
transitions.
power-off
as to which power
configuration
of a valid VP=
Therefore,
or after
after normal
or
or lock-bit
or WSM
circuitry
the GUI
array is
lock-bit
or
against
to V,
Upon
LRS13023
Vcc
are
the
D
increases usable battery
In
extremely
power is applied.. For example,
products
use an array of devices
consume
standby or sleep,modes.
devices can be read following
wake-up cycles required
See AC
Operations
information.
A system designer must guard against spurious
for V,eoltages
both WE and m must be low for a comman
driving
two-step
added level of protection
In-system
inadvertent
while m=V,,
5.6 Power Dissipation
When
consider battery power consumption
device operation,
system
when system power is removed.
addition,
designing
either to VIH will inhibit
idle
and other power sensitive
negligible
command
low power consumption
Characteristics-
block lock and unlock
and
data alteration.
regardless of its contro1 inputs state.
time.
deep
above Vu0
Figures
portable
but also for data retention
power by. lowering
sequence
Flash
powerdown
If access is again needed, the
after Rp isfirst
life because data is retained
against data alteration.
for solid-state
12,13 .and
systems,
Read
memory’s
when V,, is activ;.:;
The device
the tpHQv and tpHwL
architecture
portable
capability
even when system
Only
writes. The GUI’s
applications
not only during
designers
mode
14 for more
raised to V,,.
nonvolatility
storage can
and
is disabled
i?p to :VK
computing
provides
prevents
ensures
during
writes
Write
must
that
* ,
29