lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 13

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

rote: V,-,
I/O&O~
f40-419
GND
Svm
Vcc
SHARP
WE
bP
OE
_. _-
-
CE
Rp
,P, n,
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
Type
m and WE mean F-V,,,
GROUND:
data during
CHIP ENABLE:
amplifiers.
levels.
RESET/DEEP
internal
write
deep power-down
master lock-bit
set. RP=V,,,
operations
with V,,<RI’cV&
OUTPUT
WRITE ENABLE:
latched
BLOCK
erasing array blocks, writing
contents
invalid VP, (see DC Characteristics)
attempted.
DEVICE
attempts
DC Characteristics)
byte write and lock-bit
ADDRESS
are internally
DATA
float to high-impedance
internally
-
operations
INPUT/OUTPUTS:
on
ERASE, BYTE WRITE,
automation.
cannot
POWER
to the flash memory
ENABLE:
latched during
a-high
the rising
INPUTS:
to locked
Do not float any ground
memory
overrides
latched during
POWER-DOWN:
and enables configuration
be altered. Block erase, byte write, and lock-bit
Activates
which
SUPPLYDo
Controls
sets the device to read array mode. Ris at V,,
produce
produce
deselects
Gates the device’s
F-V,,,
Inputs
Table 2. Pin Descriptions
m-high
memory
edge of the WE pulse.
array, status register,
configuration
block lock-bits
provides
LRS13023
when the chip is deselected
a write
the device’s
writes
F-a,
Inputs
for addresses
spurious
spurious
bytes, or configuring
a write
the device and reduces power
enables normal operation.
blocks.
are inhibited.
not float any power
LOCK-BIT
Puts the device in deep power-down
cycle.
data protection
Fa
to the CUI and array blocks. Addresses
Name and Function
data and commands
pins.
produce
cycle.
operations
Block erase, byte write,
results and should
results and should
thereby enabling block erase and byte write
control
outputs
and F-WE.
during
of block lock-bits
CONFIGURATION
and identifier
Device operations
spurious
logic, input buffers,
during
with V,,<3.OV
during
read and write operations.
lock-bits.
pins. With VCCIVLKO,
or outputs
a read cycle.
results and should
during
power
When driven
code read cycles. Data pins
not be attempted.
not be attempted.
when the master lock-bit
consumption
With VPP5VPPLK, memory
or lock-bit
at invalid Vcc voltage (see
CUI write cycles; outputs
POWER SUPPLY:
transitions.
configuration
are disabled.
are not supported.
enables setting of the
decoders,
mode and resets
low, p
configuration
all write
and
not be
to standby
Exit from
Block erase,
Addresses
and sense
Data is
with an
data are
inhibits
For
is
11