lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 15

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

When VPPIVPPLK,
The CUI, with two-step block
lock-bit
protection
voltage
disabled when V,,
VLKO or when RP is at Vl,. The device’s block locking
capability
inadvertent
byte write operations.
3 BUS OPERATION
The local
in-system. All bus cycles to or from the flash memory
:onform to standard microprocessor
3.1 Read
Information
:odes,
voltage. RP can be at either Vl, or V,,.
The first task is to write the appropriate
:ommand
status
Tower-up or after exit from deep power-down
:he device automatically
Four control pins dictate the data flow in and out of
:he component:
>e driven active to obtain data at the outputs. m is the
device selection control, and when active enables the
ielected
ielected memory
it VI,
llustrates a read cycle.
1.2 Output Disable
Mith 0lY at a logic-high
Ire disabled.
high-impedance
I/O&O,)
SHARI=
or status
Register)
and m
configuration
is applied
memory
(Read Array, Read Identifier
from unwanted
CPU
code or data alteration
provides
can be read from any block,
control
Output
---
CE, OE, WE, and m. CE and m must
state.
must be at V,,
data onto the I/O bus. WE must be
to the CUI.
reads
register
memory contents cannot be altered.
device.
is below the write lockout voltage
to VP+. All write
pins I/0,-1/0,
and when
command
level (Vt,), the device outputs
additional
and
resets to read array mode.
operations
independent
m
writes
Upon
is the data
erase, byte write, or
sequences, provides
or V,,.
by gating erase and
active
bus cycles.
protection
are placed in a
even when high
Codes, or Read
flash
initial
functions
.c
of the VP,
drives
read mode
Figure 12
identifier
memory
output
device
mode,
LRS13023
from
the
are
may not occur because the flash memory
providing
SHARP’s
initialization
of the i?l? input. In this application,
As with any automated
Rp during system reset. When the system comes out of
reset, it expects to read from
Automated
when accessed during
lock-bit
with no flash memory
the same m
minimum
return from power-down
outputs are valid. After this wake-up interval,
operation
mode and status register is set to 80H.
During
configuration
Memory
data may be partially
required
another command
consuming
3.4 Deep Power-Down
i?Ij at V,, initiates the deep power-down
In read modes, m-low
output drivers in a high-impedance
all internal
3.3 Standby
n
standby
power consumption.
a high-impedance
deselected during
configuration,
at a logic-high
configuration
contents being altered are no longer valid; the
mode
block
after Rp goes to logic-high
is restored.
status information
of 100 ns. Time
active power until the operation
flash memories
flash
following
circuits.
modes, m-low
the device continues
signal that resets the system CPU.
which
erase,
can be written.
memories
block erase, byte write, or lock-bit
level (V,,)
state
I/O&O,
erased or written. Time tpHWL is
RP must
The CUI is reset to read array
modes.
reset, proper CPU initialization
a system reset through
device, it is important
substantially
deselects the memory,
block
byte
until initial
provide status information
independent
tPHQv is required
will abort the operation.
instead
If a CPU reset occurs
allow
erase, byte write,
outputs
places the device in
write,
be held
the flash memory.
Rp is controlled
state and turns off
functioning,
reduces
memory
of array data.
proper
mode.
are placed in
(VI,)
or
of OE.
low for a
completes.
to assert
may be
lock-bit
the use
normal
before
device
places
access
CPU
after
and
by
or
13
If