s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 52

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

52
Burst Sequence
Only sequential burst is allowed in the device. CR7 defaults to a ‘1’ and must al-
ways be set to a ‘1’.
Burst Length Configuration
The device supports four different read modes: continuous mode, and 8, 16, and
32 word linear with or without wrap around modes. A continuous sequence (de-
fault) begins at the starting address and advances the address pointer until the
burst operation is complete. If the highest address in the device is reached during
the continuous burst read mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap around begins on the starting
address written to the device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after the previous eight word
boundary, wrapping through the starting location. The sixteen- and thirty-two lin-
ear wrap around modes operate in a fashion similar to the eight-word mode.
Table 15
Burst Wrap Around
By default, the device will perform burst wrap around with CR3 set to a ‘1’.
Changing the CR3 to a ‘0’ disables burst wrap around.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising edge of the clock after the
initial synchronous access time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set so that the falling clock
edge is active for all synchronous accesses. CR6 determines this setting; “1” for
rising active (default), “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will output V
is valid data on the outputs. The device can be set so that RDY goes active one
data cycle before active data. CR8 determines this setting; “1” for RDY active
(default) with data, “0” for RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
RDY Polarity
By default, the RDY pin will always indicate that the device is ready to handle a
new transaction with CR10 set to a ‘1’ when high. In this case, the RDY pin is
active high. Changing the CR10 to a ‘0’ sets the RDY pin to be active low. In this
Burst Modes
Note: Upon power-up or hardware reset the default setting is continuous.
16-word linear
32-word linear
8-word linear
shows the CR2-CR0 and settings for the four read modes.
Continuous
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
Table 15. Burst Length Configuration
A d v a n c e
CR2
0
0
0
1
I n f o r m a t i o n
Address Bits
CR1
0
1
1
0
OH
whenever there
CR0
0
0
1
0