s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 35

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

June 28, 2004 S71WS512NE0BFWZZ_00_A1
Standby Mode
Automatic Sleep Mode
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
V
logical one.
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
not accept commands on the rising edge of WE#. The internal state machine is
automatically reset to the read mode on power-up
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are
both held at V
access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. While in synchronous mode, the au-
tomatic sleep mode is disabled. Note that a new burst operation is required to
provide new data.
I
specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading
array data. When RESET# is driven low for at least a period of t
mediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
CC3
CC6
IH
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
SS
IL
in
in
but not within V
± 0.2 V, the device draws CMOS standby current (I
“DC Characteristics”
“DC Characteristics”
A d v a n c e
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
CC
± 0.2 V. The device requires standard access time (t
ACC
SS
+ 20 ns. The automatic sleep mode is independent of the
± 0.2 V, the standby current will be greater.
I n f o r m a t i o n
represents the standby current specification.
IL
represents the automatic sleep mode current
and OE# = V
IH
during power up, the device does
IL
CC4
, CE# = V
). If RESET# is held
RP
, the device im-
IH
CE
or WE# =
) for read
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