s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 112

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

AC CHARACTERISTICS (Continued)
Notes
Notes
112
SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE)
SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE)
Clock Period
Clock High Time
Clock Low Time
Clock Rise/Fall Time
Address Setup Time to ADV# Low
Address Setup Time to CE#1 Low
Address Hold Time from ADV# High
ADV# Low Pulse Width
ADV# Low Setup Time to CLK
ADV# Low Setup Time to CE#1 Low
CE#1 Low Setup Time to CLK
ADV# Low Hold Time from CLK
Burst End ADV High Hold Time from CLK
*1: Clock period is defined between valid clock edge.
*2: Clock rise/fall time is defined between V
*1: t
*2: t
*3: Applicable to the 1st valid clock edge.
is satisfied. The both of t
ASCL
VPL
is specified from the negative edge of either CE#1 or ADV# whichever comes late.
is applicable if CE#1 brought to Low after ADV# is brought to Low under the condition where t
Parameter
Parameter
RL=5
RL=4
RL=3
ASCL
and t
ASVL
128Mb pSRAM
must be satisfied if t
IH
P r e l i m i n a r y
Symbol
Symbol
Min. and V
t
t
t
t
t
t
t
t
t
t
CKVH
t
t
ASCL
VSCK
CLCK
VHVL
ASVL
VLCL
t
AHV
CKH
CKT
VPL
CKL
CK
IL
Max.
Min.
Min.
–5
–5
10
13
13
18
30
—
5
5
5
5
1
4
4
VLCL
Value
Value
is not satisfied.
Max.
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
S71WS512NE0BFWZZ_00_A1 June 28, 2004
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
*1
*1
*2
*3
*1
*3
*3
*1
*1
*1
*2
VLCL