s71ws512ne0bfwzz Meet Spansion Inc., s71ws512ne0bfwzz Datasheet - Page 14

• Manufacturer Part Number: s71ws512ne0bfwzz
• Description: Stacked Multi-chip Product Mcp Flash Memoy And Psram Cmos 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory And Pseudo-static Ram
• Manufacturer: Meet Spansion Inc.

S29WSxxxN MirrorBit™ Flash Family
For Multi-chip Products (MCP)
S29WS256N
256 Megabit (16 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
14
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Manufactured on 110 nm MirrorBit
technology
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
— Zero latency between read and write operations
— Sixteen bank architecture: Each bank consists of
Programable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 32, 16, and 8 words with or without
— Continuous Sequential Burst
SecSi
— 256 words accessible through a command
Sector Architecture
— S29WS256N: Eight 16 Kword sectors and two-
— Banks 0 and 15 each contain 16 Kword sectors and
— Eight 16 Kword boot sectors, four at the top of the
100,000 erase cycles per sector typical
20-year data retention typical
Read access times at 66/54 MHz @ 1.8V V
- 1.95V)
— Burst access times of 11.2/13.5 ns for 1.8V V
— Synchronous initial latency of 69/69 ns for 1.8V V
— Asynchronous random access times of 70/70 ns for
High Performance
— Typical word programming time of < 40 µs
— Typical effective word programming time of <9.4 µs
— Typical effective word programming time of <4 µs
— Typical sector erase time of <150 ms for both 16
executing erase/program functions in another bank
16Mb (WS256N)
wrap-around
sequence, 128 words for the Factory SecSi Sector
and 128 words for the Customer SecSi Sector.
hundred-fifty-four 64 Kword sectors
64 Kword sectors; Other banks each contain 64
Kword sectors
address range, and four at the bottom of the
address range
30 pF at industrial temperature range)
(@ 30 pF at industrial temperature range)
1.8V V
utilizing a 32-Word Write Buffer at Vcc Level
utilizing a 32-Word Write Buffer at ACC Level
Kword sectors and <400 ms sector erase time for 64
Kword sectors
TM
(Secured Silicon) Sector region
IO
(@ 30 pF at industrial temperature range)
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP) S71WS512NE0BFWZZ_00_ A1 June 28, 2004
TM
process
A d v a n c e
IO
(1.65
IO
(@
IO
Hardware Features
Security Features
Software Features
I n f o r m a t i o n
Power dissipation (typical values, C
66 MHz
— Continuous Burst Mode Read: <28 mA
— Simultaneous Operation: <50 mA
— Program: <35 mA
— Erase: <35 mA
— Standby mode: <20 µA
Sector Protection
— Write protect (WP#) function allows protection of
Handshaking feature available
— Provides host system with minimum possible latency
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
Boot Option
— Dual Boot
CMOS compatible inputs, CMOS compatible
outputs
Low V
Advanced Sector Protection consists of the two
following modes of operation
Persistent Sector Protection
— A command sector protection method to lock
— Sectors can be locked and unlocked in-system at V
Password Sector Protection
— A sophisticated sector protection method to lock
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
Data# Polling and toggle bits
— Provides a software method of detecting program
eight outermost boot sectors, four at top and four at
bottom of memory, regardless of sector protect
status
by monitoring RDY
array data
combinations of individual sectors to prevent
program or erase operations within that sector
level
combinations of individual sectors to prevent
program or erase operations within that sector using
a user-defined 64-bit password
and erase operation completion
CC
write inhibit
L
= 30 pF) @
CC