80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 78

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80ksbr200

Manufacturer Part Number
80ksbr200
Description
Srio Serial Buffer Flow-control Device
Manufacturer
Integrated Device Technology
Datasheet
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
8.1.8 Error Management Extensions Summary
Error Management Extensions Block Header
identifies this as the error management extensions block header.
Logical/Transport Layer Error Detect CSR
if simultaneous errors are detected during the same clock cycle that the errors are logged, or if the detected errors are not
enabled for capture. LTLEDCSR is stored in each GRIO port and the Message Unit, although the values in this register can
differ for each port/Message Unit. A port’s LTLEDCSR cannot detect any errors if the port or the Message Unit has
captured an enabled Logical/Transport layer error until the detected error is cleared, and likewise, the Message Unit’s
LTLEDCSR cannot detect any errors if the Message Unit or any port has captured an enabled Logical/Transport layer
error. Software should write this register with all 0’s to clear the detected error and unlock the capture registers in all ports/
Message Unit. Undefined results will occur if this register is written or read while actual Logical/Transport Layer errors are
being detected by the port (where detect cannot occur if an error has already been detected and not yet cleared).
bits are enabled, capture is done on a priority basis. If PRT is set and enabled, and multiple bits are detected in
LTLEDCSR, the capture information corresponds to PRT. If PRT is not set or not enabled, then all set and enabled
LTLEDCSR bits correspond to the captured packet.
be saved in the top port /Message Unit in the PBUS daisy chain that detected an enabled error, and the set and enabled
detect bits of the port(s)/Message Unit below will be masked from the PBUS daisy chain. This means that a read of
LTLEDCSR will only return the un-enabled set bits from any port/Message Unit and enabled set bits from the top port /
Message Unit in the daisy chain with a set enabled error, and that a read of the capture registers will return the values in
the top port /Message Unit in the daisy chain with a set enabled error; i.e., the set enabled detect bits will correspond to the
capture registers.
Note:
Name:
Name:
The error management extensions block header register contains the EF_PTR to the next EF_BLK and the EF_ID that
This register indicates the error detected by the Logical or Transport logic layer. Multiple bits may get set in the register
If a port detects multiple errors in the same cycle, multiple LTLEDCSR bits will be set to reflect this. If one or all of these
If more than one port or Message Unit detects one or more enabled errors in the same cycle, the capture registers will
15:0
31:16
2:0
3
Bit
Bit
The above register is described in the RIO Specification Part 8, sec. 2.3.2.1
ERR_MGMT_BLK_HDR
LTL_ERR_DET_CSR
EXT_FEAT_ID
EXT_FEAT_PTR
-
TRSP_SZE_ERR
Field Name
Field Name
Table 35 Error Management Extensions Block Header
Table 36 Logical/Transport Layer Error Detect CSR
0x0007
0x0000
0
1b0
Reset
Value
Reset
Value
78 of 172
Address:
Address:
Extended Features ID:
Hard wired extended features ID.
Extended Features Pointer:
Hard wired pointer to the next block in the data structure.
Reserved.
Transport Size Error:
The tt field is nor consistent with bit 27 of the Processing Element
Features CAR (i.e., the tt value is reserved or indicates a common
transport system that is unsupported by this device).
0x000600
0x000608
Comment
Comment
Advanced Datasheet*
March 19, 2007

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