80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 63

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
8.0 Registers
uration and flag registers.
parts. The programming of the configuration registers are described in the section on system initialization. When using
sRIO, the configuration registers are accessible only through maintenance packets. They cannot be accessed by using
NWRITE, NREAD or SWRITE.
once configured, so these should be separated from configurations that may change. It is more likely that destination IDs
and other soft configurations will change, especially in large applications that are not adequately served by four output
queues on a port.
port that will not kill itself in process.
sRIO specification. An example is the Error Management registers that may be found in the RapidIO Part 8: Error Manage-
ment Extension Specification and in the “Error Handling” section of this document.
8.1 sRIO Registers
configuration, and status of a processing element using this logical specification. All registers are 32-bits and aligned to a
32-bit boundary.
8.1.1 Register Summary
and status registers (CSRs) can be accessed using RapidIO maintenance operations. Any register offsets not defined are
considered reserved for this specification unless otherwise stated. Other registers required for a processing element are
defined in other applicable RapidIO specifications and by the requirements of the specific device and are beyond the
scope of this specification. Read and write accesses to reserved register offsets shall terminate normally and not cause an
error condition in the target device. Writes to CAR (read-only) space shall terminate normally and not cause an error condi-
tion in the target device.
8.1.2 Extended Features Data Structure
extended features bit (bit 28) in the processing element features register is set, the extended features pointer is valid and
points to the first entry in the extended features data structure. This pointer is an offset into the standard 16 Mbyte capa-
bility register (CAR) and command and status register (CSR) space and is accessed with a maintenance read operation in
the same way as when accessing CARs and CSRs.
to the next structure (EF_PTR) and an extended feature type identifier (EF_ID). The end of the list is determined when the
next extended feature pointer has a value of logic 0. All pointers and extended features blocks shall index completely into
the extended features space of the CSR space, and all shall be aligned to a double-word boundary so the three least
significant bits shall equal logic 0. Pointer values not in extended features space or improperly aligned are illegal and shall
be treated as the end of the data structure.
The registers of the SerB are grouped into functions. Register types include the following:
In the sRIO world, the term CSR is used for “Command and Status Registers”. These are the combination of the config-
All registers are accessible by S-Port, I
As a further grouping, the electrical characteristics of the ports and presence of external memory should remain fixed
The configuration registers are broken into blocks of related functions that may be read by any port and written by any
It should be noted that in addition to the registers shown here, others exist that are described elsewhere and in the
This chapter describes the visible register set that allows an external processing element to determine the capabilities,
Table below shows the register map for this RapidIO specification. These capability registers (CARs) and command
The RapidIO capability and command and status registers implement an extended capability data structure. If the
The extended features data structure is a singly linked list of double-word structures. Each of these contains a pointer
sRIO Registers (CARs and CSRs)
SerB Configuration Registers
SerB Error Counter Registers
SERDES Control Registers
Flag & Flag Mask Registers
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C and JTAG. Not all parts of the registers are necessarily accessed from all
Advanced Datasheet*
March 19, 2007