80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 139

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
15.5 Instruction Register (IR)
tion is then used to select the test to be performed or the test register to be accessed, or both. The instruction shifted into
the register is latched at the completion of the shifting process, when the TAP controller is at the Update-IR state.
to perform the following functions:
15.5.1 EXTEST
the SAMPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from or load values onto the external
pins of the 80KSBR200. Once this instruction is selected, the user then uses the SHIFT-DR TAP controller state to shift
values into the boundary scan chain. When the TAP controller passes through the UPDATE-DR state, these values will be
latched onto the output pins or into the output enables.
The Instruction register allows an instruction to be shifted serially into the SerB at the rising edge of TCK. The instruc-
The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded
The Instruction Register is comprised of 4 bits to decode instructions, as shown in the table below.
The external test (EXTEST) instruction is used to control the boundary scan register, once it has been initialized using
EXTEST
SAMPLE/
PRELOAD
IDCODE
HIGHZ
CLAMP
EXTEST_PULSE
EXTEST_TRAIN
RESERVED
CONFIGURA-
TION REGISTER
ACCESS (CRA)
PRIVATE
SHIFT FUSE
STATUS
PRIVATE
BYPASS
Instruction
To select test data registers that may operate while the instruction is current. The other test data registers
should not interfere with chip operation and selected data registers.
To define the serial test data register path used to shift data between TDI and TDO during data register
scanning.
Table 104 Instructions Supported By 80KSBR200’s JTAG Boundary Scan
Mandatory instruction allowing the testing of board level interconnections. Data is typi-
cally loaded onto the latched parallel outputs of the boundary scan shift register using
the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST
will then hold these values on the outputs while being executed. Also see the CLAMP
instruction for similar capability.
Mandatory instruction that allows data values to be loaded onto the latched parallel out-
put of the boundary-scan shift register prior to selection of the other boundary-scan test
instruction. The Sample instruction allows a snapshot of data flowing from the system
pins to the on-chip logic or vice versa.
Provided to select Device Identification to read out manufacturer’s identity, part, and
version number.
Tri-states all output and bidirectional boundary scan cells.
Provides JTAG user the option to bypass the part’s JTAG controller while keeping the
part outputs controlled similar to EXTEST.
AC Extest instruction implemented in accordance with the requirements of the IEEE
std. 1149.6 specification.
AC Extest instruction implemented in accordance with the requirements of the IEEE
std. 1149.6 specification.
Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1 specifi-
cation. However, the user is advised to use the explicit BYPASS instruction.
SerB-specific opcode to allow reading and writing of the configuration registers. Reads
and writes must be 32-bits. See further detail below.
For internal use only. Do not use.
To shift the internal fuse status out to TDO pin.
For internal use only. Do not use.
The BYPASS instruction is used to truncate the boundary scan register as a single bit in
length.
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Definition
Advanced Datasheet*
0000
0001
0010
0011
0100
0101
0110
0111 — 1001
1010
1011 — 1100
1101
1110
1111
OPcode
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