80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 69

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
of a processing element through regular read and write operations rather than maintenance operations. The double-word
offset is right-justified in the register. As is the case with all registers, an external processor writing to LCSBA1CSR should
not assume it has been written until a response has been received.
Base Device ID CSR
sRIO according to the sRIO specification. There are locations for both 8 and 16 bit device IDs as described in the RapidIO,
Part 3, Common Transport Specification in section 3.5.1. The SerB shall allow programming of both, in order to allow both
8 and 16 bit operations simultaneously. Both device IDs may be read by any of the interfaces with access to the configura-
tion registers.
as Load Configuration will have no affect on the Base Device ID CSR. The Base Device ID CSR has no shadow register.
Host Base Device ID Lock CSR
responsible for initializing this processing element. The HBDID field is a write-once/resettable field which provides a lock
function. Once the HBDID field is written, all subsequent writes to the field are ignored, except in the case that the value
written matches the value contained in the field. In this case, the register is re-initialized to 0xFFFF. After writing the HBDID
field, a processing element must then read the host base device ID lock CSR to verify that it owns the lock before
attempting to initialize this processing element.
Note:
Note:
Name:
Name:
The sRIO searchable source and destination IDs are contained in the Base Device ID CSR, and are programmed by
The device IDs are cleared only by Master Reset or by a specific write to the Base Device ID CSR. Other resets, such
Note: This register is in the sRIO spec and that spec overrides this info.
The host base device ID lock CSR contains the base device ID value for the processing element in the system that is
16:0
30:17
31
16:0
30:17
31
Bit
Bit
1.
1.
LCL_CONF_ADDR_1_CSRAddress:
BASE_DEV_ID_CSR
The above register is described in the RIO Specification Part 1, sec. 5.5.3
The above register is described in the RIO Specification Part 3, sec. 3.5.1
-
LCL_BASE_ADDR
-
LRG_BASE_DEVID
BASE_DEVID
-
Field Name
Field Name
Table 21 Local Configuration Space Base Address 1 CSR
0
0x 0000
0
0xFFFF
0xFF
0
Reset
Value
Reset
Value
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Address:
Table 22 Base Device ID CSR
Reserved.
Local Configuration Space Base Address:
These bits correspond to the highest 14 bits of the 34-bit RIO
address space.
Reserved.
Large Base Device ID:
SerB Source/Destination ID is 16 bits. The Base ID of the device in a
large common transport system. This field is valid only if bit 27 of the
Processing Element Features CAR is set.
Base Device ID:
SerB Source/Destination ID is 8 bits. The Base ID of the device in a
small common transport system (RIO device ID)
Reserved.
0x00005C
0x000060
Comment
Comment
Advanced Datasheet*
March 19, 2007