80ksbr200 Integrated Device Technology, 80ksbr200 Datasheet - Page 118

• Manufacturer Part Number: 80ksbr200
• Description: Srio Serial Buffer Flow-control Device
• Manufacturer: Integrated Device Technology

„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Notes
12.2.1 Interfacing to Standard-, Fast-, and Hs-mode devices
SerB supports Hs- and Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I
specification for detail on speed negotiation on a mixed speed bus.
12.2.2 SerB Specific Memory Access
memory address to be explicitly specified during writes. This provides directed memory accesses through the I
Subsequent reads always begin at the address specified during the last write.
Thus, the following are required: device address – one or two bytes depending on 10-bit/7-bit addressing, memory address
– 3 bytes yielding 22-bits of memory address, and a 32-bit data payload – 4 byte words.
access would be to perform a write operation and issue a repeated start after the acknowledge bit following the third byte
of memory address. Then, the master would issue a read command selecting the SerB through the standard device
address procedure with the R/W bit high. Note that in 10-bit device address mode (ADS=1), only the two MSBs need be
provided during this read. Data from the previously loaded address would immediately follow the device address protocol.
It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final
acknowledge (i.e. canceling the write before the actual write operation is completed and performed). Also, the master
would be allowed to access other devices attached to the I
read operation from the loaded address.
12.3 Figures
Note:
The SerB supports Fast / Standard (F/S) modes of operation. Per I
There is a SerB-specific I
The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address.
The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper
1 1 1 0
1.
1 1 1 0
2 LSBs associated with word and byte pointers are DON’T CARE and are therefore not transmitted.
R/W Bit (R=1, W=0)
I
2
C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the
Address
R/W Bit (R=1, W=0)
Device
[9:8]
Address
Device
[9:8]
1 A
1
8
A
8
2
C memory access implementation. This implementation is fully I
Figure 16 Write protocol with 10-bit Slave Address (ADS =1)
Figure 17 Read Protocol with 10-bit Slave Address (ADS=1)
MSB Byte
MSB Byte
Word #1
Word #1
Data
Data
118 of 172
17
17
A
A
Data output is from base mem_addr[21:0]
Data output is from base mem_addr[21:0]
Word #1
Byte #2
Word #1
Data
Byte #2
Data
2
C bus before returning to select the SerB for the subsequent
26
A
2
26
A
C specification, in mixed speed communication the
Word #1
Byte #3
Data
Word #1
Byte #3
Data
35
A
35
A
2
Advanced Datasheet*
C compliant. It requires the
LSB Byte
Word #1
Data
LSB Byte
Word #1
March 19, 2007
Data
5686 drw05
44
A
2
C bus.
44
A
2
C