am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 29

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

SBHE
System Bus High Enable
This signal indicates the HIGH byte of the system data
bus is to be used. There is a weak pull-up resistor on
this pin. If the PCnet-ISA II controller is installed in an
8-bit only system like the PC/XT, SBHE will always be
HIGH and the PCnet-ISA II controller will perform only
8-bit operations. There must be at least one LOW going
edge on this signal before the PCnet-ISA II controller
will perform 16-bit operations.
SD0-15
System Data Bus
This bus is used to transfer data to and from the PC-
net-ISA II controller to system resources via the ISA
data bus. SD0-15 is driven by the PCnet-ISA II
controller when performing slave read operations.
Likewise, the data on SD0-15 is latched by the PC-
net-ISA II controller when performing slave write
operations.
Board Interface
APCS/IRQ15
Address PROM Chip Select
This signal is asserted when the external Address
PROM is read. When an I/O read operation is per-
formed on the first 16 bytes in the PCnet-ISA II
controller’s I/O space, APCS is asserted. The outputs
of the external Address PROM drive the PROM Data
Bus. The PCnet-ISA II controller buffers the contents of
the PROM data bus and drives them on the lower eight
bits of the System Data Bus. IOCS16 is not asserted
during this cycle.
BPAM
Boot PROM Address Match
This pin indicates a Boot PROM access cycle. If no
Boot PROM is installed, this pin has a default value of
HIGH and thus may be left connected to V
BPCS
Boot PROM Chip Select
This signal is asserted when the Boot PROM is read. If
BPAM is active and MEMR is active, the BPCS signal
will be asserted. The outputs of the external Boot
PROM drive the PROM Data Bus. The PCnet-ISA II
controller buffers the contents of the PROM data bus
and drives them on the System Data Bus. IOCS16 is
not asserted during this cycle. If 16-bit cycles are
performed, it is the responsibility of external logic to
assert MEMCS16 signal.
Input
Input/Output
Output
Input
Output
DD
.
Am79C961A
DXCVR/EAR
Disable Transceiver/
External Address Reject
This pin disables the transceiver. The DXCVR output is
configured in the initialization sequence. A high level
indicates the Twisted Pair Interface is active and the
AUI is inactive, or SLEEP mode has been entered. A
low level indicates the AUI is active and the Twisted Pair
interface is inactive.
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and tim-
ing of this signal).
LED0-3
LED Drivers
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0
continues to indicate 10BASE-T Link Status. The
DXCVR input becomes the EAR input.
PRAB0-15
Private Address Bus
The Private Address Bus is the address bus used to
drive the Address PROM, Remote Boot PROM, and
SRAM.
PRDB3-7
Private Data Bus
This is the data bus for the static RAM, the Boot PROM,
and the Address PROM.
PRDB2/EEDO
Private Data Bus Bit 2/Data Out
A multifunction pin which serves as PRDB2 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA OUT from the EEPROM.
LED
1
2
3
EADI Function
SRDCLK
SF/BD
Input/Output
Output
SRD
Input/Output
Input/Output
Input/Output
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