am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 112

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

CSR96-97: Bus Interface Scratch Register 0
Bit
31-0
CSR98-99: Bus Interface Scratch Register 1
Bit
31-0
CSR104-105: SWAP
Bit
31-0
112
Internal Write Operation
SWAP
SCR0
SCR1
Lower 16-Bit
Name
Name
Name
32-Bit word
(CSR104)
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor
tions between the BIU and BMU
are written and read through
SCR0 and SCR1 registers. The
SCR0 register is undefined until
written.
Read/write accessible only when
STOP or SPND bits are set.
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All
Descriptor
tions between the BIU and BMU
are written and read through
SCR0 and SCR1 registers.
Read/write
when STOP or SPND bits are
set.
This register performs word and
byte swapping depending upon
if 32-bit or 16-bit internal write
operations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is
externally accessible for test
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
Read/write
when STOP or SPND bits are
set.
SRC[31:16] SWAP[15:0]
SRC[15:0] SWAP[31:16]
SRC[15:8] SWAP[7: 0]
SWAP Register Result
SRC[7:0] SWAP[15:8]
Description
Description
Description
Data
Data
accessible
accessible
communica-
communica-
only
only
Am79C961A
CSR108-109: Buffer Management Scratch
Bit
31-0 BMSCR
CSR112: Missed Frame Count
Bit
15-0
CSR114: Receive Collision Count
Bit
15-0
CSR124: Buffer Management Unit Test
Bit
15-5
4
GPSIEN
RCVCC
Name
Name
Name
Name
MFC
RES
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management
BMSCR register is undefined
until written.
Read/write
when STOP bit is set.
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC
increments to 0 and sets MFC0
bit (CSR4.9).
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and
sets RCVCC0 bit (CSR4.5)
This register is used to place the
BMU/BIU
modes to support Test/Debug.
This register is writeable when
the ENTST bit in CSR4 is set.
Reserved locations. Written as
zero and read as undefined.
This mode places the PCnet-ISA
II controller in the GPSI Mode.
Description
Description
Description
Description
into
accessible
Test
various
Modes.
only
test