am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 116

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

4
3
2
1,0
116
ISAINACT
EADISEL
MEDSEL
AWAKE
LED
1
2
3
is
10BASE5_SEL bit is set and the
AUI port is active, the DXCVR is
driven such that an external
DC-DC
disabled. The actual polarity of
the DXCVR pin is determined by
the DXCVRP bit in PnP Register
0xF0.
When the 10BASE-T port is
active, this bit has no effect.
10BASE5_SEL is reset to ZERO.
ISAINACT allows for reduced
inactive timing appropriate for
modern ISA machines. ISAINACT
is cleared when RESET is assert-
ed. When ISAINACT is a zero,
tMMR3 and tMMW3 parameters
are nominally 200 ns, which is
compatible with EISA system.
When ISAINACT is set by writing
a one, tMMR3 and tMMW3 are
nominally set to 100 ns.
EADI Select. Enables EADI
match mode.
When EADI mode is selected,
the pins named LED1, LED2,
and LED3 change in function
while LED0 continues to indicate
10BASE-T Link Status.
Auto-Wake. If AWAKE = “1", the
10BASE-T receive circuitry is
active during sleep and listens
for Link Pulses. LED0 indicates
Link Status and goes active if the
10BASE-T port comes out of
“link fail” state. This LED0 pin
can be used by external circuitry
to re-enable the PCnet-ISA II
controller and/or other devices.
When AWAKE = “0", the Au-
to-Wake circuity is disabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Media Select. It was previously
defined as ASEL (Auto Select)
and XMAUSEL (External MAU
Select) in the PCnet-ISA. They
are now combined together and
defined to be software compatible
active.
converter
EADI Function
SRDCLK
SF/BD
SRD
When
will
Am79C961A
the
be
ISACSR3: EEPROM Configuration
Bit
15
14
13–5
4
3
MEDSEL
0
0
1
1
EE_VALID
SHFBUSY
EE_LOAD
EE_EN
Name
N/A
(1:0)
0
1
0
1
Software Select (Mode Reg, CSR15)
10BASE-T Port
Auto Selection (Default)
AUI Port
with ASEL and XMAUSEL in the
PCnet-ISA (Am79C960).
EEPROM Valid. This bit is a
read-only register. When a one
is read, EE_PROM has a valid
checksum. The sum of the total
bytes reads should equals FF
hex. When a zero is read, check-
sum failed, or SHFTBUSY pin
was sampled with a zero which
indicates no EEPROM present.
EEPROM Load. When written
with a one, the device will load
the EEPROM into the PC-
net-ISA II, performing self con-
figuration. This command must
be last write to ISACSR3 Regis-
ter. PCnet-ISA II will not respond
to any slave commands while
loading the EEPROM register.
EE_LOAD will be reset with a
zero after EEPROM is read. It
takes approximately, 1.4 ms for
serial EEPROM load process to
complete.
Reserved. Read and written as
zeros.
EEPROM Enable. When EE_EN
is written with a one, the lower
three bits of PRDB becomes SK,
DI and DO, respectively. EECS
and SHFBUSY are controlled by
the software select bits. This bit
must be written with a one to
write to or read from the EE-
PROM. PCnet-ISA II should be
in the STOP state when EE_EN
is written. When EE_EN is
cleared, DI/DO, SK, EECS and
SHFBUSY have no control.
Shift Busy. SHFBUSY allows for
the control of the SHFBUSY pin.
When a one is written, SHFBUSY
goes high provided EE_EN is a 1.
When a zero is written, SHF-
BUSY is held to a zero. When
EE_EN is cleared, SHFBUSY will
maintain the last value pro-
grammed. (Refer to Bit 4 above,
Description
Function