am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 28

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTION: BUS SLAVE MODE
ISA Interface
AEN
Address Enable
This signal must be driven LOW when the bus performs
an I/O access to the device.
IOCHRDY
I/O Channel Ready
When the PCnet-ISA II controller is being accessed, a
HIGH on IOCHRDY indicates that valid data exists on
the data bus for reads and that data has been latched
for writes.
IOCS16
I/O Chip Select 16
When an I/O read or write operation is performed, the
PCnet-ISA II controller will drive this pin LOW to indi-
cate that the chip supports a 16-bit operation at this
address. (If the motherboard does not receive this
signal, then the motherboard will convert a 16-bit
access to two 8-bit accesses).
The PCnet-ISA II controller follows the IEEE P996 spec-
ification that recommends this function be implemented
as a pure decode of SA0-9 and AEN, with no depen-
dency on IOR, or IOW; however, some PC/AT clone
systems are not compatible with this approach. For this
reason, the PCnet-ISA II controller is recommended to
be configured to run 8-bit I/O on all machines. Since data
is moved by memory cycles there is vir tually no
performance loss incurred by running 8-bit I/O and
compatibility problems are virtually eliminated. The PC-
net-ISA II controller can be configured to run 8-bit-only I/
O by clearing Bit 0 in Plug and Play Register F0.
IOR
I/O Read
To perform an Input/Output Read operation on the
device IOR must be asserted. IOR is only valid if the
AEN signal is LOW and the external address matches
the PCnet-ISA II controller’s predefined I/O address
location. If valid, IOR indicates that a slave read opera-
tion is to be performed.
IOW
I/O Write
To perform an Input/Output write operation on the
device IOW must be asserted. IOW is only valid if AEN
signal is LOW and the external address matches the
PCnet-ISA II controller’s predefined I/O address loca-
tion. If valid, IOW indicates that a slave write operation
is to be performed.
28
Input
Output
Input/Output
Input
Input
Am79C961A
IRQ3, 4, 5, 9, 10, 11, 12, 15
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON or TXSTRT. All status flags have a mask
bit which allows for suppression of IRQ assertion.
These flags have the following meaning:
MEMR
Memory Read
ME M R go es L OW to pe rfo r m a me mo r y r ea d
operation.
MEMW
Memory Write
MEMW goes LOW to perform a memory write opera-
tion.
REF
Memory Refresh
When REF is asserted, a memory refresh cycle is in
progress. During a refresh cycle, MEMR assertion
is ignored.
RESET
Reset
When RESET is asserted HIGH, the PCnet-ISA II
controller performs an internal system reset. RESET
must be held for a minimum of 10 XTAL1 periods before
being deasserted. While in a reset state, the PCnet-ISA
II controller will tristate or deassert all outputs to
predefined reset levels. The PCnet-ISA II controller
resets itself upon power-up.
SA0-15
System Address Bus
This bus carries the address inputs from the system
address bus. Address data is stable during command
active cycle.
BABL
RCVCCO
JAB
MISS
MERR
MPCO
RINT
IDON
TXSTRT
Babble
Receive Collision Count Overflow
Jabber
Missed Frame
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
Output
Input
Input
Input
Input
Input