am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 109

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

CSR70-71: Temporary Storage
Bit
31-0
CSR72: Receive Ring Counter
Bit
15-0
CSR74: Transmit Ring Counter
Bit
15-0
CSR76: Receive Ring Length
Bit
15-0
RCVRC
XMTRC
RCVRL
TMP8
Name
Name
Name
Name
Temporary Storage location.
Read/write
when STOP or SPND bits are
set.
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write
when STOP or SPND bits are
set.
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write
when STOP or SPND bits are
set.
Receive Ring Length. Contains
the Two’s complement of the
receive descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initial-
ization routine based on the
value in the RLEN field of the ini-
tialization block. This register
can be manually altered; the
actual receive ring length is
defined by the current value in
this register.
Description
Description
Description
Description
accessible
accessible
accessible
only
only
only
Am79C961A
CSR78: Transmit Ring Length
Bit
15-0
CSR80: Burst and FIFO Threshold Control
Bit
15-14
13-12RCVFW[1:0]
XMTRL
Name
Name
RES
Read/write
when STOP or SPND bits are
set.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-ISA II controller initial-
ization routine based on the
value in the TLEN field of the ini-
tialization block. This register
can be manually altered; the
actual transmit ring length is
defined by the current value in
this register.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Read as
ones. Written as zero.
Receive
RCVFW controls the point at
which ISA bus receive DMA is
requested in relation to the num-
ber of received bytes in the
receive FIFO. RCVFW specifies
the number of bytes which must
be present (once the frame has
been verified as a non-runt)
before receive DMA is request-
ed. Note however that, if the net-
work interface is operating in
half-duplex mode, in order for
receive DMA to be performed for
a new frame, at least 64 bytes
must have been received. This
effectively avoids having to react
to receive frames which are
runts or suffer a collision during
the slot time (512 bit times). If
the Runt Packet Accept feature
is enabled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write
when STOP or SPND bits are
set.
Description
Description
FIFO
accessible
accessible
accessible
Watermark.
only
only
only
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