am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 20

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

ler when performing bus master writes and slave read
operations. Likewise, the data on SD0-15 is latched by
the PCnet-ISA II controller when performing bus
master reads and slave write operations.
Board Interface
IRQ12/FlashWE
Flash Write Enable
Optional interface to the Flash memory boot PROM
Write Enable.
IRQ15/APCS
Address PROM Chip Select
When programmed as APCS in Plug and Play Register
F0, this signal is asserted when the external Address
PROM is read. When an I/O read operation is
performed on the first 16 bytes in the PCnet-ISA II con-
troller’s I/O space, APCS is asserted. The outputs of
the external Address PROM drive the PROM Data Bus.
The PCnet-ISA II controller buffers the contents of the
PROM data bus and drives them on the lower eight bits
of the System Data Bus.
When programmed to IRQ15 (default), this pin has the
same function as IRQ 3, 4, 5, 9, 10, 11, or 12.
BPCS
Boot PROM Chip Select
This signal is asserted when the Boot PROM is read. If
SA0-19 lines match a predefined address block and
MEMR is active and REF inactive, the BPCS signal will
be asserted. The outputs of the external Boot PROM
drive the PROM Data Bus. The PCnet-ISA II controller
buffers the contents of the PROM data bus and drives
them on the lower eight bits of the System Data Bus.
DXCVR/EAR
Disable Transceiver/
External Address Reject
This pin can be used to disable external transceiver
circuitry attached to the AUI interface when the internal
10BASE-T port is active. The polarity of this pin is set
by the DXCVRP bit (PnP register 0xF0, bit 5). When
DXCVRP is cleared (default), the DXCVR pin is driven
HIGH when the Twisted Pair port is active or SLEEP
mode has been entered and driven LOW when the AUI
port is active. When DXCVRP is set, the DXCVR pin is
driven LOW when the Twisted Pair port is active or
SLEEP mode has been entered and driven HIGH when
the AUI port is active.
20
Output
Output
Output
Input/Output
Am79C961A
If EADI mode is selected, this pin becomes the EAR
input.
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the
result of this check will be OR’d with the value on the
EAR pin. The EAR pin is defined as REJECT. (See the
EADI section for details regarding the function and
timing of this signal).
LEDO-3
LED Drivers
These pins sink 12 mA each for driving LEDs. Their
meaning is software configurable (see section The ISA
Bus Configuration Registers) and they are active LOW.
When EADI mode is selected, the pins named LED1,
LED2, and LED3 change in function while LED0
continues to indicate 10BASE-T Link Status.
PRDB3-7
Private Data Bus
This is the data bus for the Boot PROM and the
Address PROM.
PRDB2/EEDO
Private data bus bit 2/Data Out
A multifunction pin which serves as PRDB2 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA OUT from the EEPROM.
PRDB1/EEDI
Private data bus bit 1/Data In
A multifunction pin which serves as PRDB1 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become DATA In to the EEPROM.
PRDB0/EESK
Private data bus bit 0/
Serial Clock
A multifunction pin which serves as PRDB0 of the
private data bus and, when ISACSR3 bit 4 is set,
changes to become Serial Clock to the EEPROM.
LED
1
2
3
EADI Function
SRDCLK
SF/BD
SRD
Output
Input/Output
Input/Output
Input/Output
Input/Output