am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 21
am79c961a
Manufacturer Part Number
am79c961a
Description
Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C961A.pdf
(206 pages)
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SHFBUSY
Shift Busy
This pin indicates that a read from the external
EEPROM is in progress. It is active only when data is
being shifted out of the EEPROM due to a hardware
RESET or assertion of the EE_LOAD bit (ISACSR3, bit
14). If this pin is left unconnected or pulled low with a
pull-down resistor, an EEPROM checksum error is
forced. Normally, this pin should be connected to V
through a 10K
EECS
EEPROM CHIP SELECT
This signal is asserted when read or write accesses
are being performed to the EEPROM. It is controlled by
ISACSR3. It is driven at Reset during EEPROM Read.
SLEEP
Sleep
When SLEEP pin is asserted (active LOW), the PC-
net-ISA II controller performs an internal system reset
pull-up resistor.
Input/Output
Output
Input
Am79C961A
CC
and proceeds into a power savings mode. All outputs
will be placed in their normal reset condition. All PC-
net-ISA II controller inputs will be ignored except for the
SLEEP pin itself. Deassertion of SLEEP results in the
device waking up. The system must delay the starting
of the network controller by 0.5 seconds to allow inter-
nal analog circuits to stabilize.
XTAL1
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Alternatively, an
external 20 MHz CMOS-compatible clock signal can be
used to drive this pin. Refer to the section on External
Crystal Characteristics for more details.
XTAL2
Crystal Connection
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock is used, this pin should be left unconnected.
Input
Output
21