zl50407 Zarlink Semiconductor, zl50407 Datasheet - Page 67

• Manufacturer Part Number: zl50407
• Description: Lightly Managed/unmanaged 8-port 10/100m + 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.1.6
CPU Address:h037
Accessed by CPU (R/W)
13.3.2
13.3.2.1
I²C Address 028; CPU Address:h100
Accessed by CPU and I²C (R/W)
13.3.2.2
I²C Address 029; CPU Address:h101
Accessed by CPU and I²C (R/W)
13.3.2.3
I²C Address 02A, CPU Address:h102
Accessed by CPU and I²C (R/W)
This register indicates the legal egress ports. A “1” on bit 3 means that the packet can be sent to port 3. A “0” on bit
3 means that any packet destined to port 3 will be discarded. This register works with registers 1 to form a 10 bit
mask to all egress ports.
13.3.2.4
I²C Address h34, CPU Address:h103
Accessed by CPU and I²C (R/W)
(Group 1 Address) VLAN Group
FCC – Flow Control Grant Period
AVTCL – VLAN Type Code Register Low
AVTCH – VLAN Type Code Register High
PVMAP00_0 – Port 0 Configuration Register 0
PVMAP00_1 – Port 0 Configuration Register 1
Bit [2:0]:
Bit [7:3]:
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
Bit [1:0]:
Bit [7:2]:
VLANType_LOW: Lower 8 bits of the VLAN type code (Default 0)
VLANType_HIGH: Upper 8 bits of the VLAN type code (Default is 0x81)
Flow Control Grant Period (Default 0x3)
Reserved
VLAN Mask for port 0 (Default 0xFF)
VLAN Mask for ports 9 to 8 (Default 0x3)
Reserved (Default 0x3F)
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ZL50407
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Data Sheet