zl50407 Zarlink Semiconductor, zl50407 Datasheet - Page 109

• Manufacturer Part Number: zl50407
• Description: Lightly Managed/unmanaged 8-port 10/100m + 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.11.3
CPU Address: hF02
Accessed by CPU (RO)
13.3.11.4
CPU Address:hF03
Accessed by CPU (R/W)
13.3.11.5
CPU Address: hF04
Accessed by CPU (RO)
This register provides various internal information as selected in DPST bit [4:0]. Refer to the PHY Port Control
Application Note, ZLAN-37.
Bit [6:0]
Bit [7]
Bit [4:0]:
Bit [7:5]:
Bit [0]
Bit [1]
Bit [2]
Bit [3]
Bit [4]
Bit [5]
Bit [6]
Bit [7]
DCR1 - Device Status Register 1
DPST – Device Port Status Register
DTST – Data read back register
Reserved
Chip initialization completed
Read back index register. This is used for selecting what to read back from
DTST. (Default 00)
Reserved
Flow control enable
Full duplex port
Fast Ethernet port (if bit [5] not set)
Link is down
Auto negotiation enabled
1: Disable
0: Enable
Gigabit Ethernet port
Reserved
Module deleted (for hot swap purpose)
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-
-
-
-
-
-
-
-
-
5’b00000 - Port 0 Operating mode and Negotiation status
5’b00001 - Port 1 Operating mode and Negotiation status
5’b00010 - Port 2 Operating mode and Negotiation status
5’b00011 - Port 3 Operating mode and Negotiation status
5’b00100 - Port 4 Operating mode and Negotiation status
5’b00101 - Port 5 Operating mode and Negotiation status
5’b00110 - Port 6 Operating mode and Negotiation status
5’b00111 - Port 7 Operating mode and Negotiation status
5’b01000 - Port CPU Operating mode and Negotiation status
5’b01001 - Port GMAC Operating mode and Negotiation status
Zarlink Semiconductor Inc.
ZL50407
109
Data Sheet