zl50407 Zarlink Semiconductor, zl50407 Datasheet

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... One 10/100/1000 Mbps auto-negotiating port with GMII & MII interface options, that can be used as a WAN uplink 9th port • Operates stand-alone or can be cascaded with a second ZL50407 to reach 16 ports • Embedded 2 Mbits (256 KBytes) internal memory • supports byte frames • ...

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... Backpressure flow control for Half Duplex ports • Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-In Self Test for internal SRAM • IEEE-1149.1 (JTAG) test port ZL50407 2 Zarlink Semiconductor Inc. Data Sheet ...

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... UDP/TCP logical port fields in IP packets. The ZL50407 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50407 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link. ...

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... Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 MAC Address Filtering 5.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.8 Priority Classification Rule 5.9 Port Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ZL50407 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...

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... JTAG Test Clock (TCK) speed requirements 11.2 Clock Generation 11.2.1 MDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.2.2 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2.3 Ethernet Interface Clocks 12.0 Hardware Statistics Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 IEEE 802.3 HUB Management (RFC 1516 12.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.3 FCSErrors 12.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 ZL50407 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...

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... CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.9 Jabbers 12.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 ZL50407 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.2 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.3 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.4 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2.5 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.2.6 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.2.7 Control Command Frame Buffer2 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13 ...

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... RDRC2 – WRED Rate Control 13.3.6.8 SFCB – Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.3.6.9 C1RS – Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.3.6.10 C2RS – Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.3.6.11 C3RS – Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.3.6.12 AVPML – VLAN Tag Priority Map 13.3.6.13 AVPMM – VLAN Priority Map ZL50407 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...

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... Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3.8.1 MIRROR CONTROL – Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.3.8.2 MIRROR_DEST_MAC[5:0] – Mirror Destination MAC Address 0 13.3.8.3 MIRROR_SRC _MAC[5:0] – Mirror Source MAC Address 0 13.3.8.4 RMAC_MIRROR0 – RMAC Mirror 13.3.8.5 RMAC_MIRROR1 – RMAC Mirror ZL50407 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...

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... Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.1 Absolute Maximum Ratings 111 14.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.4.2 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.4.3 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ZL50407 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...

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... MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14.4.7 I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 14.4.8 Serial Interface Setup Timing 121 14.4.9 JTAG (IEEE 1149.1-2001 122 15.0 Document Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.1 July 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.2 November 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.3 February 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 15.4 August 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ZL50407 10 Zarlink Semiconductor Inc. Data Sheet ...

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... M2_RX M2_C M2_TX M3_RX M3_C 1.2 Power and Ground Distribution G7-10, H7-10, J7-10, K7-10 GND 3.3V D5, D12, E4, E13, M4, M13, N5 1.8V D9, H4, H13, N7 ZL50407 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD TSTO TSTO TSTO TSTO TSTO ...

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... L13, K14, L15, L16, M[7:0]_RXD[3:0] Input N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, R8, T8, N4, P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 K16, T15, T12, T9, T5, M[7:0]_CRS_DV Input T2, L1, H1 ZL50407 I/O 2 Output Serial Clock Line w/ pull up Unmanaged Mode Only 2 I/O-TS I ...

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... B16 M9_RXCLK C14, D14, D13, E14, M9_RXD[7:0] F14, F13, G14, G13 A16 M9_TXEN B15 M9_TXER ZL50407 I/O Output, slew Ports [7:0] – Transmit Enable This pin also serves as a bootstrap pin. Output, slew Ports [7:0] – Transmit Data Bit [3:0] Input Ports[7:0] – Collision w/ pull down Input or Output Ports[7:0] – ...

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... V DD D5, D12, E4, E13, M4 M13, N5, G7-10, H7-10, J7-10 K7-10 Misc. D1 RESIN# C1 RESETOUT# ZL50407 I/O Input Transmit Clock w/ pull up Output Gigabit Transmit Clock Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Input JTAG - Test Data In ...

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... B8, A7, B7, A6, B6, A5, B5, B4 Bootstrap Pins (1= pull up 0= pull down) D2 TSTOUT[0] D3, C2 TSTOUT[2:1] C3 TSTOUT[3] C5, C4, D4 TSTOUT[6:4] C6 TSTOUT[7] D7 TSTOUT[8] ZL50407 I/O Output MII Management Data Clock I/O-TS MII Management Data I/O w/ pull up Input RMAC Reference Clock Input GMAC Reference Clock w/ pull up N/A Reserved. Leave unconnected. 1 Input (Reset Only) Enable Debounce of STROBE signal Pullup – ...

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... A16, B15 M9_TXEN, M9_TXER 1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for pull-downs. ZL50407 I/O Input (Reset Only) Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose) ...

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... Signal Mapping and Internal Pull Up/Down Configuration The ZL50407 Fast Ethernet access ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in the “Ball Signal Description Table” on page 12. It also specifies whether the internal pull up/down resistor is present for each pin in the specific operating mode ...

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... The ZL50407 Gigabit Ethernet uplink port (port 9) supports 2 interface options: GMII & MII. The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in “Ball Signal Description Table” on page 12. ...

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... C EEPROM can be used to configure the device at power-up or reset. TSTOUT[7] selects the EEPROM option. The ZL50407 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) and M9-TXEN & M9_TXER (port 9) are used to specify the module type to support multiple ethernet interfaces during module hotswap ...

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... Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M), Reverse MII, or Reverse GPSI (only for 10M). The RMAC of the ZL50407 device meets the IEEE 802.3 specification able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for total transmissions ...

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... Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface, which offers a simple migration from 10/100 to 1G. The GMAC of the ZL50407 device meets the IEEE 802.3Z specification able to operate in 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism Full duplex mode with flow control mechanism ...

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... Heartbeat Packet Generation and Response The ZL50407 provides the ability to monitor a link and detect a simple link failure. The Link Heart Beat (LHB) packet generation module allows simultaneous tracking of all the RMAC ports. Periodically, a LHB message will be sent for each link when inactivity is detected with in a programmable time period reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link ...

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... Register Configuration The ZL50407 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The device allows indirect access to these registers, as follows: • ...

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... The speed of the serial interface limits management capability. For example, if the system is trying to implement port security, it would require a faster interface between the CPU and the ZL50407, such as the 8/16-bit interface or the serial + MII interface found on the managed device. 3.1.3 ...

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... Start Condition Generated by the master (in our case, the ZL50407). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I² ...

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... I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time bits are used to allow up to eight ZL50407 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. ...

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... STROBE- fall. 3.3.1 Write Command All registers in ZL50407 can be modified through this synchronous serial interface. Once the data has been sent, two extra STOBE clocks must be generated to indicate the end of the write command. The DATAIN line should be held high for these two pulses. ...

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... CPU ports, to map the 8 transmit priorities into 4 multicast queues, the LSB is discarded. The priority mapping can be modified through memory configuration command. The multicast queue that is in FIFO format shares the space in the internal memory block. The size and starting address can also be programmed through memory configuration command. ZL50407 28 Zarlink Semiconductor Inc. Data Sheet ...

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... Basic Flow Shortly after a frame enters the ZL50407 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding ...

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... This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. MAC address filtering allows the ZL50407 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem ...

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... Extensive core QoS mechanisms are built into the ZL50407 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue (WFQ) scheduling at the egress port. In the ZL50407, QoS-based policies sort traffic into a small number of classes and mark the packets accordingly. The QoS identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class ...

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... Definition” on page 52). For example, ports 1-3 might be assigned to the Marketing VLAN, ports 4-6 to the Engineering VLAN, and ports 7-9 to the Administrative VLAN. The ZL50407 determines the VLAN membership of each packet by noting the port on which it arrives. From there, the ZL50407 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. ...

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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. 6.2 Frame Engine Details This section briefly describes the functions of each of the modules of the ZL50407 frame engine. 6.2.1 FCB Manager The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure. ...

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... Table 7 shows examples of QoS applications with three transmission priorities, but best effort (P0) traffic may form a fourth class with no bandwidth or latency assurances. GMAC port actually has four total transmission priorities. ZL50407 34 Zarlink Semiconductor Inc. ...

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... It is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. In the ZL50407, each RMAC port will support two total classes, and the GMAC port will support four classes. We will discuss the various modes of scheduling these classes in the next section ...

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... Although traffic shaping is not a primary function of the ZL50407, the chip does implement a shaper for every queue in the GMAC port. Our goal in shaping is to control the average rate of traffic exiting the ZL50407. If shaper is enabled, strict priority will be applied to that queue. The priority between two shaped queue is the same as in strict priority scheduling ...

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... Though we do have global resource management nothing other than per port WRED to prevent this situation locally. We assume the traffic is policed at a prior stage to the ZL50407 or WRED dropping is fine and shall restrain this situation. ...

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... Such a temporary region is necessary, because when the frame first enters the ZL50407, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. This ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying ...

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... Xon is triggered when a port is currently being flow controlled, and all of that port’s reserved FDB slots have been released. Note that the ZL50407’s per-source-port FDB reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. ...

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... On the receiving side, the MAC will also monitor the activity. If there is no good packet received for more than 2X the set period, an alarm will be raised to the CPU. The LHB packet is only used by the ZL50407 to reset the timeout counter ignored otherwise (i.e. not passed on within the system). ...

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... Features and Restrictions A port group (i.e. trunk) can include physical ports, all of the ports in a group can be in the same ZL50407 or in multiple ZL50407 to form a fault tolerant link. There are eight trunk groups total. Load distribution among the ports in a trunk for unicast is performed using hashing based on source MAC address and destination MAC address ...

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... Up to two ports can be setup as mirrored ports result, the traffic (both ingress and egress specific port can be monitored by setting up both mirrored ports. Once a port is setup as mirrored port, it cannot be used for regular traffic. The mirrored port can be any port in the ZL50407. 9.2 Using port mirroring for loop back To perform remote loop back test, port mirroring can be used to bounce back the packet to the source port to check the data path ...

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... VLAN is supported with GPSI interface. 11.0 Clocks 11.1 Clock Requirements 11.1.1 System Clock (SCLK) speed requirement SCLK is the primary clock for the ZL50407 device. The speed requirement is based on the system configuration. Below is a table for a few configuration. Configuration 8 Port 10/100M + 1 port 1000M 6-9 ports 10/100M 1-5 ports 10/100M 11.1.2 RMAC Reference Clock (M_CLK) speed requirement M_CLK MHz clock used for the RMAC ports (ports 0-7) ...

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... Hardware Statistics Counters List ZL50407 hardware provides a full set of statistics counters for each Ethernet port. The CPU accesses these counters through the CPU interface. All hardware counters are rollover counters. When a counter rolls over, the CPU is interrupted, so that long-term statistics may be kept. The MAC detects all statistics, except for the delay exceed discard counter (detected by buffer manager) and the filtering counter (detected by queue manager) ...

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... Drop B[26] E-u Filtering Counter B[27] F-l Delay Exceed Discard Counter B[28] F-U1 Late Collision B[29] F-U Notation: X-Y Address in the contain memory X: Size and bits for the counter Y: D Word counter d: 24 bits counter bit [23: bits counter bit [31:24 bits counter bit [23:16] U1: ZL50407 45 Zarlink Semiconductor Inc. Data Sheet ...

Page 46

... No collisions 12.2.1.4 AlignmentErrors Counts number of valid frames received with bad alignment (not byte-aligned). Frame size: No framing error No collisions ZL50407 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) > 64 bytes, < ...

Page 47

... Frame size: 12.2.1.9 LateEvents Counts number of collision events that occurred late (after LateEventThreshold = 64 bytes). Frame size: Events are also counted by collision counter ZL50407 > 64 bytes, > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) don’t care don’t care < 10 bytes don’ ...

Page 48

... InDiscards Counts number of valid frames received which were discarded (i.e., filtered) by the forwarding process. 12.3.1.4 DelayExceededDiscards Counts number of frames discarded due to excessive transmit delay through the bridge. 12.3.1.5 MtuExceededDiscards Counts number of frames discarded due to excessive size. ZL50407 > Jabber 48 Zarlink Semiconductor Inc. Data Sheet ...

Page 49

... Counts number of frames received with FCS or alignment errors Frame size: No collisions: 12.4.1.6 UndersizePkts Counts number of frames received with size less than 64 bytes. Frame size: No FCS error No framing error No collisions ZL50407 > 64 bytes, < 1522 bytes if VLAN Tagged; (< 1518 bytes if not VLAN Tagged) < 64 bytes, 49 Zarlink Semiconductor Inc. Data Sheet ...

Page 50

... Pkts256to511Octets for any packet with size from 256 bytes to 511 bytes Pkts512to1023Octets for any packet with size from 512 bytes to 1023 bytes ZL50407 > 1522 bytes if VLAN Tagged; (> 1518 bytes if not VLAN Tagged) don’t care don’t care < ...

Page 51

... Miscellaneous Counters In addition to the statistics groups defined in previous sections, the ZL50407 has other statistics counters for its own purposes. We have two counters for flow control – one counting the number of flow control frames received, and another counting the number of flow control frames sent. We also have two counters, one for unicast frames sent, and one for non-unicast frames sent. A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “ ...

Page 52

... Register Definition 13.1 ZL50407 Register Description Register 0. ETHERNET Port Control Registers (Substitute [n] with Port number (0..9)) ECR1Pn Port Control Register 1 for Port n ECR2Pn Port Control Register 2 for Port n ECR3Pn Port Control Register 3 for Port n ECR4Pn Port Control Register 4 for Port n BUF_LIMIT Frame Buffer Limit ...

Page 53

... CPURLSINFO[4:0] CPUGRNCTR 4. Search Engine Configurations AGETIME_LOW MAC Address Aging Time Low AGETIME_HIGH MAC Address Aging Time High SE_OPMODE Search Engine Operating Mode Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) 229+2n 300 301 302 303 304 305 306 310+n 323 ...

Page 54

... Well Known Logic Port 2 and 3 Priority WLPP54 Well Known Logic Port 4 and 5 Priority WLPP76 Well Known Logic Port 6 and 7 Priority WLPE Well Known Logic Port Enable Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) 500 510 511 512 513 514 515 518 ...

Page 55

... MII Command Register 0 MIIC1 MII Command Register 1 MIIC2 MII Command Register 2 MIIC3 MII Command Register 3 MIID0 MII Data Register 0 MIID1 MII Data Register 1 Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) 565 570+2n 571+2n 590 591 592 593 594 595 ...

Page 56

... Address 4 MIRROR_DEST_MAC5 Mirror Destination MAC Address 5 MIRROR_SRC_MAC0 Mirror Source MAC Address 0 MIRROR_SRC_MAC1 Mirror Source MAC Address 1 MIRROR_SRC_MAC2 Mirror Source MAC Address 2 Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) 609 60A 60B 610 611 612 613 614 620 621 622 ...

Page 57

... Port Threshold for GMAC Port QOSCn QOS Control n E. System Diagnostic DTSRL Test Register Low DTSRM Test Register Medium TESTOUT0 Testmux Output [7:0] TESTOUT1 Testmux Output [15:8] Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) 709 70A 70B 70C 710 711 800+n 820+n 840+n 848 ...

Page 58

... FCB Tail Pointer [7:0] FCB_TAIL_PTR1 FCB Tail Pointer [15:8] FCB_NUM0 FCB Number [7:0] FCB_NUM1 FCB Init Start and FCB Number [14:8] BM_RLSFF_CTRL Read control register BM_RLSFF_INFO0 Bm_rlsfifo_info[7:0] Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) E10 E11 E12 E13 E14 E80-E82 E90+n EA0+n EA8 ...

Page 59

... Global Control Register DCR Device Control Register DCR1 Device Control Register 1 DPST Device Port Status Register DTST Data read back register DA DA Register Table 12 - Register Description (continued) ZL50407 CPU Addr Description (Hex) EC9 ECA ECB ECC ECD F00 F01 F02 F03 ...

Page 60

... Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. Bit [5]: Set this bit to re-start the data that is sent from the CPU to Receive FIFO (re-align). This feature can be used for software debug. For normal operation must be '0'. Bit [7:6]: Reserved. Must be '0' ZL50407 60 Zarlink Semiconductor Inc. Data Sheet ...

Page 61

... Data is read from the Control Command Frame Transmit Buffer1 13.2.7 Control Command Frame Buffer2 Access Register • CPU receive control frames (16 bits) • Address = 7 (read only) • When CPU reads this register: Data is read from the Control Command Frame Transmit Buffer2 ZL50407 61 Zarlink Semiconductor Inc. Data Sheet ...

Page 62

... Bit [7: Spanning tree state (IEEE 802.1D spanning tree protocol Blocking Listening Learning Forwarding: ZL50407 Frame is dropped Frame is dropped Frame is dropped. Source MAC address is learned. Frame is forwarded. Source MAC address is learned. (Default) 62 Zarlink Semiconductor Inc. ...

Page 63

... Bit [5:4] Reserved, Must be 0. Bit [7:6] Security Enable. The ZL50407 checks the incoming data for one of the following conditions: • If the source MAC address of the incoming packet is in the MAC table and is defined as secure address but the ingress port is not the same as the port associated with the MAC address in the MAC table. • ...

Page 64

... In this mode, the packet is looped back in the MAC layer before going out of the chip. You must force linkup at full duplex as well. External loopback is another level of system diagnostic which involves the PHY device to loopback the packet. Bit [4:3]: Interface mode GPSI mode 01 - MII mode 10 - Reserved 11 - RMII mode (Default) ZL50407 64 Zarlink Semiconductor Inc. Data Sheet ...

Page 65

... This is not the same as an ingress MAC loopback. The destination MAC address has to be stored (learned) in the MCT and associated with the originating source port. The frame loopback will only work for unicast packets. Bit [6]: Reserved Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. ZL50407 65 Zarlink Semiconductor Inc. Data Sheet ...

Page 66

... The frame loopback will only work for unicast packets. Bit [6]: Reserved Bit [7]: Soft reset. 0: Normal operation (Default) 1: Reset. Not self clearing. 13.3.1.5 BUF_LIMIT – Frame Buffer Limit CPU Address:h036 Accessed by CPU (R/W) Bit [6:0]: Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40) Bit [7]: Reserved ZL50407 66 Zarlink Semiconductor Inc. Data Sheet ...

Page 67

... This register works with registers 1 to form a 10 bit mask to all egress ports. 13.3.2.4 PVMAP00_1 – Port 0 Configuration Register 1 I²C Address h34, CPU Address:h103 Accessed by CPU and I²C (R/W) Bit [1:0]: VLAN Mask for ports (Default 0x3) Bit [7:2]: Reserved (Default 0x3F) ZL50407 67 Zarlink Semiconductor Inc. Data Sheet ...

Page 68

... I²C Address: h048, CPU Address:h170 Accessed by CPU and I²C (R/W) Bit [0]: Reserved. Must be 0. Bit [1]: Slow learning (Default = 0) Same function as SE_OP MODE bit [7]. Either bit can enable the function; both need to be turned off to disable the feature. ZL50407 68 Zarlink Semiconductor Inc. Data Sheet ...

Page 69

... Trunk Group – eight RMAC ports can be selected for each trunk group. 13.3.3.1 TRUNKn– Trunk Group 0~7 CPU Address:h200 trunk group) Accessed by CPU (R/W) Bit [7:0] Port 7-0 bit map of trunk n. (Default ZL50407 TRUNK0 Zarlink Semiconductor Inc. Data Sheet ...

Page 70

... Hash result 5 destination port number (Default 0) 13.3.3.5 TRUNKn_HASH76 – Trunk group 0~7 hash result 7/6 destination port number CPU Address:h20B+ trunk group) Accessed by CPU (R/W) Bit [3:0] Hash result 6 destination port number (Default 0) Bit [7:4] Hash result 7 destination port number (Default 0) ZL50407 70 Zarlink Semiconductor Inc. Data Sheet ...

Page 71

... Hash Select. The hash algorithm selected is valid for all trunks (Default 00 Use Source and Destination MAC Address for hashing 01 - Use Source MAC Address for hashing 10 - Use Destination MAC Address for hashing 11 - Use Source Port Number for hashing MULTICAST_HASH[7:1]-1 Reserved (Default 0x3) ZL50407 HASH0-1 HASH0-0 HASH1-1 HASH1-0 HASH2-1 HASH2-0 ...

Page 72

... CPU Address:h303 Accessed by CPU (R/W) Bit [7:0]: Byte 3 of the CPU MAC address (Default 0) 13.3.4.5 MAC4 – CPU MAC address byte 4 CPU Address:h304 Accessed by CPU (R/W) Bit [7:0]: Byte 4 of the CPU MAC address (Default 0) ZL50407 MAC3 MAC2 MAC1 MAC0 72 Zarlink Semiconductor Inc. Data Sheet 0 (MC bit) ...

Page 73

... Reserved Bit [4]: Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic counter wraps around. Refer to hardware statistic counter for interrupt sources. Bit [5]: Port 1 link change mask Bit [6]: Port 1 module detect mask Bit [7] Reserved ZL50407 73 Zarlink Semiconductor Inc. Data Sheet ...

Page 74

... Unicast Queue not empty Bit [7:4]: Multicast Queue not empty 13.3.4.12 MAC01 – Increment MAC port 0,1 address CPU Address:h325 Accessed by CPU (RW) Bit [2:0]: Bit [42:40] of Port 0 MAC address Bit [3]: Reserved Bit [6:4]: Bit [42:40] of Port 1 MAC address Bit [7]: Reserved ZL50407 74 Zarlink Semiconductor Inc. Data Sheet ...

Page 75

... MAC67 – Increment MAC port 6,7 address CPU Address:h328 Accessed by CPU (RW) Bit [2:0]: Bit [42:40] of Port 6 MAC address Bit [3]: Reserved Bit [6:4]: Bit [42:40] of Port 7 MAC address Bit [7]: Reserved 13.3.4.16 MAC9 – Increment MAC port 9 address CPU Address:h329 Accessed by CPU (RW) Bit [7:0]: Bit [47:40] of Port 9 MAC address ZL50407 75 Zarlink Semiconductor Inc. Data Sheet ...

Page 76

... Insertion Fail (May be due to queue full, WRED or filtering) Bit [1]: 13.3.4.19 CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer CPU Address:h338-339 Accessed by CPU, (RO) 15 CG1 CG0 CPU Queue insertion command Granule pointer. Bit [14:0]: Pointer valid Bit [15]: ZL50407 CQ3 CQ2 CQ1 0 76 Zarlink Semiconductor Inc. Data Sheet 0 CQ0 ...

Page 77

... AGETIME_LOW – MAC address aging time Low I²C Address h049; CPU Address:h400 Accessed by CPU and I²C (R/W) Used in conjuction with AGETIME_HIGH. The ZL50407 removes the MAC address from the data base and sends a Delete MAC Address Control Command to the CPU. Bit [7:0]: Low byte of the MAC address aging timer (Default 0x5C) 13 ...

Page 78

... Learning is performed independent of search demand (Default) 13.3.6 (Group 5 Address) Buffer Control/QOS Group 13.3.6.1 QOSC – QOS Control I²C Address h04B; CPU Address:h500 2 Accessed by CPU and I C (R/W) Bit [0]: Enable TX rate control (on RMAC ports only) 1 – Enable 0 – Disable (Default) ZL50407 78 Zarlink Semiconductor Inc. Data Sheet ...

Page 79

... MCCTH – Multicast Threshold Control CPU Address: 512 Accessed by CPU (R/W) Threshold on the multicast granule count. Exceeding the threshold consider as Bit [7:0]: multicast resource low and the new multicast will be dropped flow con- trol is triggered if enabled. (Default: 0x3) ZL50407 79 Zarlink Semiconductor Inc. Data Sheet ...

Page 80

... Bits[7:4]: Corresponds to the frame drop percentage RA% for rate control. Granularity 6.25%. 13.3.6.8 SFCB – Share FCB Size I²C Address h074, CPU Address 518 Accessed by CPU and I²C (R/W) Bits [7:0]: Expressed in multiples of 16 granules. Buffer reservation for shared pool. ZL50407 80 Zarlink Semiconductor Inc. Data Sheet ...

Page 81

... VLAN priority field. For example, programming a value of 7 into bit 2:0 of the AVPML register would map packet VLAN priority 0 into Internal transmit priority 7. The new priority is used inside the ZL50407. When the packet goes out it carries the original priority. Bit [2:0]: ...

Page 82

... Frame drop priority when VLAN Tag priority field is 4 (Default 0) Bit [5]: Frame drop priority when VLAN Tag priority field is 5 (Default 0) Bit [6]: Frame drop priority when VLAN Tag priority field is 6 (Default 0) Bit [7]: Frame drop priority when VLAN Tag priority field is 7 (Default 0) ZL50407 82 Zarlink Semiconductor Inc. Data Sheet ...

Page 83

... Map TOS into frame discard when low priority buffer usage is above threshold Bit [0]: Frame drop priority when TOS field is 0 (Default 0) Bit [1]: Frame drop priority when TOS field is 1 (Default 0) Bit [2]: Frame drop priority when TOS field is 2 (Default 0) ZL50407 83 Zarlink Semiconductor Inc. Data Sheet ...

Page 84

... Enable Protocol 7 Force Discard User Defined Logical Ports and Well Known Ports The ZL50407 supports classifying packet priority through layer 4 logical port information. It can be setup by 8 Well Known Ports, 8 User Defined Logical Ports, and 1 User Defined Range. The 8 Well Known Ports supported are: • ...

Page 85

... I²C Address h0AA, CPU Address 562 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for Well known port 4 (111 for sun remote procedure call) Bits[7:4]: Priority setting, transmission + dropping, for Well known port 5 (22555 for IP Phone call setup) ZL50407 85 Zarlink Semiconductor Inc. Data Sheet ...

Page 86

... Bits[3]: Enable Well Known Port 3 Force Discard Bits[4]: Enable Well Known Port 4 Force Discard Bits[5]: Enable Well Known Port 5 Force Discard Bits[6]: Enable Well Known Port 6 Force Discard Bits[7]: Enable Well Known Port 7 Force Discard ZL50407 86 Zarlink Semiconductor Inc. Data Sheet ...

Page 87

... USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority I²C Address h0A4, CPU Address 592 Accessed by CPU and I²C (R/W) Bits[3:0]: Priority setting, transmission + dropping, for logic port 4 Bits[7:4]: Priority setting, transmission + dropping, for logic port 5 (Default 00) ZL50407 Zarlink Semiconductor Inc. Data Sheet ...

Page 88

... Enable User Port 2 Force Discard Bits[3]: Enable User Port 3 Force Discard Bits[4]: Enable User Port 4 Force Discard Bits[5]: Enable User Port 5 Force Discard Bits[6]: Enable User Port 6 Force Discard Bits[7]: Enable User Port 7 Force Discard ZL50407 88 Zarlink Semiconductor Inc. Data Sheet ...

Page 89

... RLOW and RHIGH form a range for logical ports to be classified with priority specified in RPRIORITY. Bits[0]: Drop Priority (inclusive only) Bit [3:1] Transmit Priority (inclusive only) Bit [5:4] Reserved Bit [7: Filtering 01 - Exclusive Filtering (x<=RLOW or x>=RHIGH Inclusive Filtering (RLOW<x<RHIGH Invalid ZL50407 89 Zarlink Semiconductor Inc. Data Sheet ...

Page 90

... Bit [2]: Support DS EF Code. 0 – Disable (Default) 1 – Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. Bit [3]: Reserved. Must be 0. Bit [4]: Reserved. Must be 1. ZL50407 90 Zarlink Semiconductor Inc. Data Sheet ...

Page 91

... Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY, and no VALID; then program MII command. 13.3.7.5 MIIC1 – MII Command Register 1 CPU Address:h604 Accessed by CPU (R/W) Bits[7:0]: MII Command Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. ZL50407 91 Zarlink Semiconductor Inc. Data Sheet ...

Page 92

... MII command. Writing this register will initiate a serial management cycle to the MII management interface. 13.3.7.8 MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU (RO) Bits[7:0]: MII Data [7:0] 13.3.7.9 MIID1 – MII Data Register 1 CPU Address:h608 Accessed by CPU (RO) Bits[7:0]: MII Data [15:8] ZL50407 92 Zarlink Semiconductor Inc. Data Sheet ...

Page 93

... The checksum formula is: FF Σ I²C register = When the ZL50407 boots from the EEPROM the checksum is calculated and the value must be zero. If the checksum is not zeroed the ZL50407 does not start and pin CHECKSUM_OK is set to zero. ZL50407 93 Zarlink Semiconductor Inc. ...

Page 94

... I²C Address 0C0, CPU Address:h621 Accessed by CPU and I²C (R/W) Bit [7:0] FCB Base address bit 15:8 (Default 0x60) 13.3.7.18 FCB Base Address Register 2 I²C Address 0C1, CPU Address:h622 Accessed by CPU and I²C (R/W) Bit [7:0] FCB Base address bit 23:16 (Default 0) ZL50407 94 Zarlink Semiconductor Inc. Data Sheet ...

Page 95

... RMAC_MIRROR0 – RMAC Mirror 0 CPU Address 710 Accessed by CPU (R/W) Bit [2:0]: Source port to be mirrored Bit [3]: Mirror path 0: Receive 1: Transmit Bit [6:4]: Destination port for mirrored traffic Bit [7]: Mirror enable ZL50407 DEST_MAC3 DEST_MAC2 DEST_MAC1 [31:24] [23:16] [15:8] (Default 00) (Default 00) (Default 00) SRC_MAC3 SRC_MAC2 SRC_MAC1 [31:24] [23:16] [15:8] ...

Page 96

... To disable this function, program U2MR to 0. (Default = 0) Bit [6:4]: Time Base for Unicast to Multicast, Multicast and Broadcast rate control of Port n: (Default = 000) 000 = 100us 001 = 200us 010 = 400us 011 = 800us 100 = 1.6ms 101 = 3.2ms 110 = 6.4ms 111 = 12.8ms Bit [7]: Reserved ZL50407 96 Zarlink Semiconductor Inc. Data Sheet ...

Page 97

... PTH100_CPU – Port CPU Threshold I²C Address h0CB, CPU Address 868 Accessed by CPU and I²C (R/W) Expressed in multiples of 16 granules. More than this number used on a source port will trigger either random drop or flow control (Default 0x3) ZL50407 97 Zarlink Semiconductor Inc. Data Sheet ...

Page 98

... Multiple of 16 granules. The two numbers set the two level for WRED on the high priority queue. When the queue size exceeds the L1 threshold, received frame will subject to X% (high drop (low drop) WRED. When the queue size exceeds L2 threshold, received frame will either be filtered (high drop) or subject to Z% WRED. ZL50407 2 C Address h088, CPU Address 890) ...

Page 99

... NOTE: Device Manufacturing test registers. 13.3.10.1 DTSRL – Test Output Selection CPU Address E00 Accessed by CPU (R/W) Test group selection for testout[7:0]. 13.3.10.2 DTSRM – Test Output Selection CPU Address E01 Accessed by CPU (R/W) Test group selection for testout[15:8]. ZL50407 99 Zarlink Semiconductor Inc. Data Sheet ...

Page 100

... TX FSM NOT idle for 5 sec Bit [0]: TX FIFO control NOT idle for 5 sec Bit [1]: RX SFD detection NOT idle for 5 sec Bit [2]: RXINF NOT idle for 5 sec Bit [3]: ZL50407 15 BT2 BT1 BT0 Bit [6:0]: TSTOUT[6:0] Bit [8:7]: Invert of TSTOUT[8:7] Bit [9]: TSTOUT[11] Bit [10]: TSTOUT[9] ...

Page 101

... L1 WRED level Bit [5]: priority queue 1 reach L2 WRED level Bit [6]: priority queue 2 reach L1 WRED level Bit [7]: priority queue 2 reach L2 WRED level Bit [8]: priority queue 3 reach L1 WRED level Bit [9]: priority queue 3 reach L2 WRED level ZL50407 0 PQSTA 101 Zarlink Semiconductor Inc. Data Sheet ...

Page 102

... Priority queue 3 reach L1 WRED level Bit [9]: Priority queue 3 reach L2 WRED level Bit [10]: Priority 0 MC queue full Bit [11]: Priority 1 MC queue full Bit [12]: Priority 2 MC queue full Bit [13]: Priority 3 MC queue full Bit [15:14]: Reserved ZL50407 0 PQSTA 102 Zarlink Semiconductor Inc. Data Sheet ...

Page 103

... CPU Address EB0+n Accessed by CPU (R/W) Bit [0]: Suspend port scheduling (no departure) Bit [1]: Reset queue Bit [4:2]: Reserved Bit [5]: Force out MAC control frame Bit [6]: Force out XOFF flow control frame Bit [7]: Force out XON flow control frame ZL50407 103 Zarlink Semiconductor Inc. Data Sheet ...

Page 104

... BMBISTR0, BMBISTR1 CPU Address EBB, EBC Accessed by CPU (RO) 13.3.10.15 BMControl CPU Address EBD Accessed by CPU (R/W) Bit [3:0]: Block Memory redundancy control 0: Use hardware detected value All others: Overwrite the hardware detected memory swap map Bit [7:4]: Reserved ZL50407 104 Zarlink Semiconductor Inc. Data Sheet ...

Page 105

... Bit [7:0] CPU address EC2 Accessed by CPU (R/W) Fcb_head_ptr[14:8]. The head pointer of free granule link that CPU assigns. Bit [6:0] Set 1 to write Bit [7] If CPU wants to write again, CPU has to clear bit 15 and then set bit 15. ZL50407 105 Zarlink Semiconductor Inc. Data Sheet ...

Page 106

... The information of BM release FIFO is relocated to registers BM_RLSFF_INFO (address ECD, ECC, ECB, ECA, EC9 and EC8). If the FIFO is not empty, CPU can read out the next by setting the bit 0. Read only happens when bit 0 is changing from ZL50407 106 Zarlink Semiconductor Inc. ...

Page 107

... Accessed by CPU (RO) Bit [4:0] Rls_count[6:2] Bit [ then It is multicast packet. Bit [7:6] Rls_src_port[1:0[ CPU address ECD Accessed by CPU (RO) Bit [1:0] Rls_src_port[3:2] Bit [3:2] Class[1:0] Bit [4] This release request is from QM directly. Bit [7:5] Entries count in release FIFO, 0 means FIFO is empty ZL50407 107 Zarlink Semiconductor Inc. Data Sheet ...

Page 108

... Busy reading configuration from I²C 0: Not busy (not reading configuration from I²C) Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bit [5:4]: Device Signature 11: ZL50407 device Bit [7:6]: Revision 00: Initial Silicon 01: Second Silicon ZL50407 108 Zarlink Semiconductor Inc. Data Sheet ...

Page 109

... Flow control enable Bit [1] Full duplex port Bit [2] Fast Ethernet port (if bit [5] not set) Bit [3] Link is down Bit [4] Auto negotiation enabled 1: Disable 0: Enable Bit [5] Gigabit Ethernet port Bit [6] Reserved Bit [7] Module deleted (for hot swap purpose) ZL50407 109 Zarlink Semiconductor Inc. Data Sheet ...

Page 110

... DA – DA Register CPU Address: hFFF Accessed by CPU (RO) Always return 8’h DA. Indicate the CPU interface or serial port connection is good. Bit [7:0] Always return DA ZL50407 110 Zarlink Semiconductor Inc. Data Sheet ...

Page 111

... Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied. 14.2 DC Electrical Characteristics V = 3.3 V +/- 10 1.8 V +/- 5% DD ZL50407 -65°C to +150°C -40°C to +85°C +125°C +2. +3. +1. + ...

Page 112

... OUT C I/O Capacitance I/O Thermal resistance with 0 air flow θ ja θ Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow θ ja Thermal resistance between junction and case θ jc ZL50407 Min. 2.4 2.0 < < OUT CC 112 Zarlink Semiconductor Inc. Data Sheet Typ. Max. ...

Page 113

... R1 Bootstrap Pins Outputs Figure 10 - Typical Reset & Bootstrap Timing Diagram Symbol Parameter R1 Delay until RESETOUT# is tri-stated R2 Bootstrap stabilization R3 RESETOUT# assertion ZL50407 Tri-Stated R3 Inputs R2 Min. Typ RESETOUT# state is then determined by the external pull-up/down resistor 1 µs 10 µs Bootstrap pins sampled on rising edge of ...

Page 114

... M[7:0]_RXD[1:0] Input Setup Time M3 M[7:0]_RXD[1:0] Input Hold Time M4 M[7:0]_CRS_DV Input Setup Time M5 M[7:0]_CRS_DV Input Hold Time M6 M[7:0]_TXEN Output Delay Time M7 M[7:0]_TXD[1:0] Output Delay Time Table Characteristics – Reduced Media Independent Interface ZL50407 M_CLK M6-max M6-min Mn_TXEN M7-max M7-min Mn_TXD[1:0] M_CLK M2 Mn_RXD M3 ...

Page 115

... Mn_RXD[3:0] Input Hold Time MM4 M[9,7:0]_CRS_DV Input Setup Time MM5 Mn_CRS_DV Input Hold Time MM6 Mn_TXEN Output Delay Time MM7 Mn_TXD[3:0] Output Delay Time Table Characteristics –Media Independent Interface ZL50407 Mn_TXCLK MM6-max MM6-min Mn_TXEN MM7-max MM7-min Mn _TXD[3:0] Mn_RXCLK MM2 Mn_RXD[3:0] ...

Page 116

... M[7:0]_RXD Input Hold Time SM4 M[7:0]_CRS_DV Input Setup Time SM5 M[7:0]_CRS_DV Input Hold Time SM6 M[7:0]_TXEN Output Delay Time SM7 M[7:0]_TXD Output Delay Time Table Characteristics –General Purpose Serial Interface ZL50407 Mn_ TXCLK SM6-max SM6-min Mn_TXEN SM7-max SM7-min Mn_TXD Mn_RXCLK SM2 ...

Page 117

... Gigabit Media Independent Interface Figure Characteristics- Gigabit Media Independent Interface (TX) Figure Characteristics – Gigabit Media Independent Interface (RX) ZL50407 M9_TXCLK G12-max G12-min M9_TXD [7:0] G13-max G13-min M9_TXEN G14-max G14-min M9_TXER M9_RXCLK M9_RXCLK G1 G2 M9_RXD[7:0] M9_RXD[7: M9_RXDV M9_RXDV G5 G6 M9_RXER M9_RXER ...

Page 118

... M9_RXER Input Hold Times G7 M9_CRS Input Setup Times G8 M9_CRS Input Hold Times G12 M9_TXD[7:0] Output Delay Times G13 M9_TXEN Output Delay Times G14 M9_TXER Output Delay Times Table Characteristics – Gigabit Media Independent Interface ZL50407 125 Mhz Min. (ns) Max. (ns ...

Page 119

... MDIO Input Setup and Hold Timing Figure 19 - MDIO Input Setup and Hold Timing Symbol Parameter D1 MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time ZL50407 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 20 - MDIO Output Delay Timing MDC=500 KHz Min ...

Page 120

... I²C Input Setup Timing Symbol Parameter S1 SDA input setup time S2 SDA input hold time S3* SDA output delay time * Open Drain Output. Low to High transistor is controlled by external pullup resistor. ZL50407 SCL S2 S1 SDA Figure 21 - I²C Input Setup Timing SCL S3-max S3-min SDA Figure 22 - I² ...

Page 121

... Dataout Figure 24 - Serial Interface Output Delay Timing Symbol Parameter D1 DATAIN setup time D2 DATAIN hold time D3 DATAOUT output delay time D4 STROBE low time D5 STROBE high time ZL50407 Figure 23 - Serial Interface Setup Timing D3-max D3-min Min. (ns µ µ µ ...

Page 122

... Symbol Parameter TCK frequency of operation TCK cycle time TCK clock pulse width TRST# assert time J1 TMS, TDI data setup time J2 TMS, TDI data hold time J3 TCK to TDO data valid ZL50407 J1 J2 Figure 25 - JTAG Timing Diagram Min. Typ. Max ...

Page 123

... INT_MASK and INTP_MASK registers should state that the default register value is 0x00 15.4 August 2004 • Added Errata List to document • Added section on SCL clock generation • Interrupt Register was incorrectly identified as read only, should be read/write • Clarified that only bit [7] is not self-clearing ZL50407 123 Zarlink Semiconductor Inc. Data Sheet ...

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... TOP VIEW SIDE VIEW c Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE 213730 ACN 14Nov02 DATE APPRD. BOTTOM VIEW b Previous package codes Dimension MIN MAX 1. 0.30 0.50 0.53 REF A2 D 16.90 17.10 E 16.90 17.10 b 0.40 0.60 e 1.00 N 208 Conforms to JEDEC MO-192 Package Code ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...