zl50407 Zarlink Semiconductor, zl50407 Datasheet - Page 66

• Manufacturer Part Number: zl50407
• Description: Lightly Managed/unmanaged 8-port 10/100m + 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

Port 9: (GMAC Port)
13.3.1.5
CPU Address:h036
Accessed by CPU (R/W)
BUF_LIMIT – Frame Buffer Limit
Bit [0]:
Bit [1]:
Bit [2]:
Bit [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [6:0]:
Bit [7]:
Reserved
Enable RXCLK output. Active high
0: Disable (Default)
1: M9_RXCLK pin becomes output in MII mode
Note: To configure port 9 with the device providing the interface clocks, you need
to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional
clock.
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40)
Reserved
00 - MII mode
11 - GMII mode (Default)
Zarlink Semiconductor Inc.
ZL50407
66
Data Sheet