zl50407 Zarlink Semiconductor, zl50407 Datasheet - Page 108

• Manufacturer Part Number: zl50407
• Description: Lightly Managed/unmanaged 8-port 10/100m + 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.11
13.3.11.1
CPU Address: hF00
Accessed by CPU (R/W)
13.3.11.2
CPU Address: hF01
Accessed by CPU (RO)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [7:5]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [5:4]:
Bit [7:6]:
(Group F Address) CPU Access Group
GCR - Global Control Register
DCR - Device Status and Signature Register
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Completed (Default = 0)
This bit is reserved in unmanaged mode.
In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is
completed and ready to forward packets. The ‘0' to '1' transition will toggle
TSTOUT[2] from low to high.
Reserved
1: Busy writing configuration to I²C
0: Not busy (not writing configuration to I²C)
1: Busy reading configuration from I²C
0: Not busy (not reading configuration from I²C)
1: BIST in progress
0: BIST not running
1: RAM Error
0: RAM OK
Device Signature
11: ZL50407 device
Revision
00: Initial Silicon
01: Second Silicon
Zarlink Semiconductor Inc.
ZL50407
108
Data Sheet