zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 88
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
zl50060gag2
Manufacturer Part Number
zl50060gag2
Description
16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50060GAG2.pdf
(99 pages)
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L/BSTo0-31
L/BSTo0-31
L/BSTo0-31
L/BSTi0-31
L/BSTi0-31
L/BSTi0-31
Note *: CK_int is the internal clock signal of 131.072MHz
8.192Mbps
4.096Mbps
2.048Mbps
8.192Mbps
4.096Mbps
2.048Mbps
CK_int *
CK_int *
FP8o
FP8i
C8o
C8i
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps)
Ch31
Ch127
Bit0
Bit1
1
Ch31
Bit0
Ch63
Bit0
Ch63
Bit0
Ch127
Bit0
0
t
t
OFBOS
IDS4
Ch0
Bit7
t
7
SOD8
t
SOD4
t
SOD2
t
t
SIS8
Ch0
Bit7
IDS8
t
SIH8
t
Zarlink Semiconductor Inc.
IDS2
Bit7
Ch0
Ch0
ZL50060/1
Bit6
6
t
SIS4
t
SIH4
88
Ch0
Bit7
Bit5
Ch0
5
Ch0
Bit7
Ch0
Bit6
Ch0
Bit6
t
SIS2
Ch0
Bit4
4
t
SIH2
Ch0
Bit3
3
Ch0
Bit5
Ch0
Bit5
Ch0
Bit2
2
Ch0
Bit6
Ch0
Bit1
1
Ch0
Bit6
Data Sheet
Ch0
Ch0
Bit4
Bit4
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