zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 18

• Manufacturer Part Number: zl50060gag2
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Microprocessor Port Signals
Pin Name
D0 - D15
A0 - A14
R/W
DTA
CS
DS
V10, Y9, W9,
Coordinates
W8, V8, W7,
W6, V6, Y5,
D5, C6, A6,
D7, C7, B7,
C8, B8, A8,
D9, B9, A9,
V9, U9, Y8,
V7, U7, Y6,
D10, C10,
ZL50061
Package
(272-ball
PBGA)
A10
B11
A11
C11
A13
W5
Coordinates
M9, M8, M7,
M6, N9, N8,
R9, R8, R7,
B9, C5, C6,
N7, N6, P9,
A1, A2, A3,
A4, A5, B5,
B6, B7, B8,
C7, C8, C9
P8, P7, P6,
Package
(256-ball
ZL50060
PBGA)
C10
R6
A8
A6
A7
Zarlink Semiconductor Inc.
ZL50060/1
Address 0 - 14 (5 V Tolerant Inputs). These pins form the
15-bit address bus to the internal memories and registers.
A0 = LSB
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with
Slew-Rate Control). These pins form the 16-bit data bus of
the microprocessor port.
D0 = LSB
and/or DS to initiate the next access.
port read and write operations. Note that a minimum of
30 ns must separate the de-assertion of DTA (to high) and
the assertion of CS and/or DS to initiate the next access.
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output). This active LOW output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold a
HIGH level. Note that a minimum of 30 ns must separate
the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
Chip Select (5 V Tolerant Input). Active LOW input used by
the microprocessor to enable the microprocessor port access.
Note that a minimum of 30 ns must separate the
de-assertion of DTA (to high) and the assertion of CS
Data Strobe (5 V Tolerant Input). This active LOW input
works in conjunction with CS to enable the microprocessor
Read/Write (5 V Tolerant Input). This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
18
Description
Data Sheet