zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 66

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zl50060gag2

Manufacturer Part Number
zl50060gag2
Description
16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
Manufacturer
Zarlink Semiconductor
Datasheet
14.6
Addresses 0043
Thirty-two Backplane Input Channel Delay Registers (BCDR0 to BCDR31) allow users to program the input
channel delay for the Backplane input data streams BSTi0-31. The maximum possible adjustment is 511 channels
and the BCDR0 to BCDR31 registers are configured as follows:
14.6.1
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane input pins. The input channel delay can be selected to be up to 511 (32 Mbps streams), 255
(16 Mbps streams), 127 (8 Mbps streams), 63 (4 Mbps streams) or 31 (2 Mbps streams) channels from the frame
boundary.
Backplane 32 Mbps Mode)
Backplane Non-32 Mbps
(where n = 0 to 31 for
Mode, n = 0 to 15 for
Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
BCDRn Bit
Backplane Channel Delay Bits 8-0 (BCD8 - BCD0)
15:9
8:0
H
to 0062
Table 27 - Backplane Input Channel Delay (BCD) Programming Table
Table 26 - Backplane Input Channel Delay Register (BCDRn) Bits
0 Channel (Default)
H
Channel Delay
509 Channels
510 Channels
Input Stream
511 Channels
2 Channels
3 Channels
4 Channels
5 Channels
1 Channel
...
Reserved
BCD[8:0]
Name
Zarlink Semiconductor Inc.
ZL50060/1
Reset
Value
0
0
66
Reserved
Must be set to 0 for normal operation
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream.
Corresponding Delay Bits
BCD8-BCD0
0 0000 0000
0 0000 0001
0 0000 0010
0 0000 0100
0 0000 0101
0 0000 0011
1 1111 1101
1 1111 1110
1 1111 1111
...
Description
Data Sheet

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