zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 86
zl50060gag2
Manufacturer Part Number
zl50060gag2
Description
16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50060GAG2.pdf
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CK_int *
Control Register.
Note *: CK_int is the internal clock signal of 131.072MHz
Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
(244ns)
(122ns)
(244ns)
(122ns)
(122ns)
FP16o
FP16o
(61ns)
FP8o
FP8o
C16o
FP8i
FP8i
C8o
C8i
Figure 26 - Input and Output Clock Timing Diagram for GCI-Bus
t
OCH16
t
ICL
t
OCL8
t
FPFB16_61
t
OCL16
t
IFPS122
t
t
FPFBF16_122
OFPW16_61
t
t
OFBOS
FPFBF8_122
t
ICH
t
OCH8
Zarlink Semiconductor Inc.
ZL50060/1
t
IFPS244
t
t
t
t
IFPW122
FPFBF8_244
OFPW8_122
OFPW16_122
86
t
FBFP16_61
t
t
IFPH122
FBFPF16_122
t
FBFPF8_122
t
IFPW244
t
t
OFPW8_244
ICP
t
OCP8
t
t
rIC
fOC16
t
rOC8
t
OCP16
t
FBFPF8_244
t
IFPH244
t
t
rOC16
fIC
t
fOC8
Data Sheet
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