zl50060gag2 Zarlink Semiconductor, zl50060gag2 Datasheet - Page 76
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zl50060gag2
Manufacturer Part Number
zl50060gag2
Description
16 K Channel Digital Switch With High Jitter Tolerance, Per Stream Rate Conversion 2, 4, 8, 16 Or 32 Mbps , 64 Input And 64 Output Streams Pin Compatible With Mt90869
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50060GAG2.pdf
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14.11.5
Address 00CC
Backplane BER Count Register contains the number of counted errors. This register is read-only.
The BBCR register is configured as follows:
14.12
14.12.1
Addresses 00CD
Thirty-two Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps.
These registers may be overridden by setting Local 32 Mbps Mode in the Control Register (via the MODE32L bit),
in which case, Local input streams 0-15 will operate at 32 Mbps and Local input streams 16-31 will be unused.
The LIBRR registers are configured as follows:
15:0
(for n=0 to
Bit
LIBRn
15:2
31)
1:0
Local Bit Rate Registers
Backplane BER Count Register (BBCR)
Local Input Bit Rate Registers (LIBRR0 - LIBRR31)
BBC[15:0]
Name
H
.
H
Reserved
LIBR[1:0]
to 00EC
Name
Table 47 - Local Input Bit Rate (LIBR) Programming Table
MODE32L
Reset
Value
H
Table 45 - Backplane BER Count Register (BBCR) Bits
.
Table 46 - Local Input Bit Rate Register (LIBRR) Bits
0
0
0
0
0
1
Reset
Value
Backplane Bit Error Rate Count
The binary value of these bits defines the Backplane Bit Error count.
If the number of errors exceeds the maximum counter value, this counter will
stay at FFFF
0
0
LIBR1
X
0
0
1
1
Reserved
Must be set to 0 for normal operation
Local Input Bit Rate
Zarlink Semiconductor Inc.
ZL50060/1
H
until the CBERB bit in the BERCR register clears it.
LIBR0
76
X
0
1
0
1
Bit rate for stream n
Description
Description
16 Mbps
32 Mbps
2 Mbps
4 Mbps
8 Mbps
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