le79128 Zarlink Semiconductor, le79128 Datasheet - Page 7

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Slave PCM Highway A has a Redundant Slave PCM Highway which can be used in parallel to PCM Highway A. When enabled,
the VCP will automatically switch between Highway A and Redundant when either highway suffers a system failure. Slave PCM
Highway A, or the Redundant Slave PCM Highway, is programmed by selecting VP_OPTION_HWY_A from the API.
Slave PCM Highway B is required for 128 channel operation. Slave PCM Highway B is programmed by selecting
VP_OPTION_HWY_B from the API. Refer to the Next Generation Carrier Chipset Hardware Design Guide for diagrams on
supported PCM Highway usage.
PCLKA
FSA
DXA
DRA
TSCXA
TSCRA
PCLKB
FSB
DXB
DRB
TSCXB
TSCRB
MPCLK
MFS
MDX
MDR
TRST
TCK
TMS
TDI
TDO
EE0
EE1
UARTTX
UARTRX
Name
Pin Name
Pin
Table 3. Le79128 VCP Device Pin Description (PCM Interface Pins)
Table 4. Le79128 VCP Device Pin Description (Debug and Development Ports)
TQFP
Pin #
69
68
66
67
65
64
70
73
75
74
81
84
6
5
4
3
TQFP
Pin #
108
118
109
119
120
110
111
94
95
LBGA
Pin #
M12
K12
M11
H12
H11
E10
J12
L12
K11
F10
L11
J11
D1
C1
B1
A1
LBGA
Pin #
C11
C10
C7
B6
C6
A5
B8
C8
B5
Reset
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
Input/Output
Input/Output
Slave PCM
Highway A
Redundant
Slave PCM
Highway
Slave PCM
Highway B
Output
Output
Type
Input
Input
Input
Input
Input
Clock input.
Framing input.
PCM data output.
PCM data input.
PCM data output
tristate control.
PCM data input
tristate control.
Clock input.
Framing input.
PCM data output.
PCM data input.
PCM data output
tristate control.
PCM data input
tristate control.
Clock input.
Framing input.
PCM data output.
PCM data input.
Microsemi Corporation - CMPG
Z/Pull-down
Z/Pull-down
Z/Pullup
Reset
Pull-up
Pull-up
Pull-up
Pull-up
Z
1
1
Le79128
2
2
2
2
7
2
2
2
Debug reset input. Tie to DVSS
through 1 KΩ resistor.
Debug clock input.
Debug mode select input.
Debug data input.
Debug data output.
Emulator control pin.
Emulator debug output pin.
Transmit pin.
Receive pin.
3
3
3
Mutually exclusive with PCLKB operation.
Mutually exclusive with FSB operation.
Mutually exclusive with DXB operation.
Mutually exclusive with DRB operation.
Mutually exclusive with TSCXB operation. This output is active
low when DXA is transmitting. The output is open-drain and is
normally inactive (high impedance). A pull-up load should be
connected to DVDD. If output not used, leave node float.
Mutually exclusive with TSCRB operation. This output is active
low when DRA is transmitting. The output is open-drain and is
normally inactive (high impedance). A pull-up load should be
connected to DVDD. If output not used, leave node float.
Mutually exclusive with PCLKA operation. If not used, tie pin to
DVSS.
Mutually exclusive with FSA operation. If not used, tie pin to
DVSS.
Mutually exclusive with DXA operation. If not used, tie pin to
DVSS.
Mutually exclusive with DRA operation. If not used, tie pin to
DVSS.
Mutually exclusive with TSCXA operation. This output is active
low when DXB is transmitting. The output is open-drain and is
normally inactive (high impedance). A pull-up load should be
connected to DVDD. If output not used, leave node float.
Mutually exclusive with TSCRA operation. This output is active
low when DRB is transmitting. The output is open-drain and is
normally inactive (high impedance). A pull-up load should be
connected to DVDD. If output not used, leave node float.
If not used, tie pin to DVSS.
Description
Description
Preliminary Data Sheet
These pins are for
Microsemi debug use only.
Refer to the Debug Interface
section for more information.
For Microsemi development
use only, leave pins float.
use only, leave pins float.
For Microsemi development