le79128 Zarlink Semiconductor, le79128 Datasheet - Page 28

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

PHYSICAL LAYER
The physical layer provides both parallel and synchronous serial interfaces. These are described in the following sections.
General Purpose Parallel Interface (GPI)
The General Purpose Parallel Interface (GPI) is an external interface of the VCP device that is used to communicate command
information and data to/from an external host processor. The GPI has several configuration options and has been architected to
connect gluelessly to a variety of external processors. Options are selected via the configuration pins, refer to
interface uses a combination of write, read, data, address, and wait strobes; thus, a dedicated clock is not needed to synchronize
the transfers. The structure of the commands and data both take the form of a command word followed by data in order to
preserve the same logical view as the Serial Peripheral Interface (SPI). This allows the host to issue the same commands to a
VCP device regardless of the physical interface.
GPI External Pin List
The pins related to the GPI are described below. Pins associated with clocks, reset, or interrupts are described in another section
Note:
Z = No state driven, high impedance.
GPI Features
The GPI has been designed to connect to a variety of external host processors. The capabilities of the GPI are enumerated below.
1. Commands and data can be transferred across the parallel interface using either separate read and write strobes or using a
2. The GPI can be configured for either 8-bit or 16-bit data bus transfers.
3. A wait strobe can be used to indicate to the external processor that the interface is available for a transfer. When the wait
4. Data byte swap allows the GPI to support big and little endian systems. (Note that the command is always evaluated as big
5. A read status register is available to the external processor by performing a read while the address pin is High. The contents
PCS
PADDR
PWAIT
PD[15:0]
(PD[7:0])
PWR
(PDS)
PRD
(PRD/WR)
Pin Name
combined read/write strobe and a data strobe.
strobe goes active, the interface is busy. The transfer will complete after the wait signal deasserts. The wait strobe pin polarity
is programmable and defaults to tri-state. Note: an external pull-up or pull-down (depending on the programmed active state)
is required.
endian, so little endian systems should byte swap the command word accordingly).
of this register contains a wait status indication, which can be used by external processors that do not support the wait pin.
Table 13. GPI Pins
Input/Output/
Parallel Interface Status (GPISTATUS)
Read GPISTATUS with PADDR High.
PAGENUM:
Output/Z
Type
Input
Input
Input
Input
Z
RSVD
D15
D7
Reset
Z
Z
RSVD
D14
D6
GPI Chip Select (active Low)
GPI Address Pin (Command or Data Indicator)
GPI Wait (Programmable polarity and drive mode, external pull-inactive required)
GPI Data Bus.
GPI Write Strobe (active Low).
Alternate configuration as GPI Data Strobe (active Low)
GPI Read Strobe (active Low).
Alternate configuration as GPI Read/Write Strobe (Read=High, Write=Low)
Alternate configuration as 8-bit Data Bus.
Current active page
RSVD
Microsemi Corporation - CMPG
D13
D5
Le79128
28
RSVD
D12
D4
PAGENUM
RSVD
D11
D3
Description
CMD_PROG
D10
D2
Preliminary Data Sheet
INT
D9
D1
Table
8. The GPI
PWAIT
D8
D0
(RO)