le79128 Zarlink Semiconductor, le79128 Datasheet - Page 25

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

MWDT:
MCFAIL GLOBAL:PLL or selected source Clock Fail mask. When asserted the interrupt is
MCFAIL PCLKA: PCLKA/FSA Clock Fail mask. When asserted the interrupt is masked.
MCFAIL PCLKB: PCLKB/FSB Clock Fail mask. When asserted the interrupt is masked.
MSYS_FLAG[9:0]: Software configurable system interrupt mask bit. When asserted the interrupt is
Boot Sense [GPIO31:16]
GPIO[31:16]:
Boot Sense [GPIO15:0]
GPIO[15:0]:
Reset Type
A four-bit value indicating the cause of the last System Reset event. The Boot Loader copies
CLKSTAT [19:16] into the low nibble of this register. See Table 12 for interpretation of these bits.
GPIO[31]
GPIO[23]
GPIO[15]
GPIO[7]
D15
D15
D15
D7
D7
D7
GPIO[30]
GPIO[22]
GPIO[14]
GPIO[6]
D14
D14
D14
D6
D6
D6
(Default = 1). If this bit is asserted (masked), the SYSSTAT must be read to
clear the OVL status. Otherwise, if the OVL is unmasked, a read of the INTIND
clears the OVL status bit.
Watch Dog Timer mask. When asserted the interrupt is masked (default = 1). If
this bit is asserted (masked), the SYSSTAT must be read to clear the WDT
status. Otherwise, if the WDT is unmasked, a read of INTIND clears the WDT
status bit.
masked. (default = 1)
(default = 1)
(default = 1)
Reset GPIO input value.
Reset GPIO input value.
masked. (default = 1)
RSVD
GPIO[29]
GPIO[21]
GPIO[13]
GPIO[5]
Microsemi Corporation - CMPG
D13
D13
D13
D5
D5
D5
Le79128
GPIO[28]
GPIO[20]
GPIO[12]
GPIO[4]
25
D12
D12
D12
D4
D4
D4
RSVD
GPIO[27]
GPIO[19]
GPIO[11]
GPIO[3]
POR
D11
D11
D11
D3
D3
D3
GPIO[18]
GPIO[10]
GPIO[26]
GPIO[2]
Direct page address 0x14 (RW)
Direct page address 0x15 (RW)
D10
D10
D10
RST
D2
D2
D2
Direct page address 0x16 (R)
Preliminary Data Sheet
GPIO[25]
GPIO[17]
GPIO[9]
GPIO[1]
WDT
D9
D1
D9
D1
D9
D1
GPIO[24]
GPIO[16]
HWRES
GPIO[8]
GPIO[0]
D8
D0
D8
D0
D8
D0